Abstract: A system and method for web-based interface design tool is provided. The design tool enables system designers to quickly and independently design a custom serial-link interface. The system provides interface selection and signal integrity analysis. An interface selection may interact with system designers to prompt for a set of selection criteria such as data-rate, supply rail, standard protocol, and intended application. An intelligent search engine screens through a large interface products database based on the selection criteria and provides designers with a list of devices that potentially meet the design criteria. The performance of the custom system with the selected device can be evaluated by using a web-based IBIS-AMI standard-compliant signal integrity simulator. A designers can have options to manually fine tune selected devices' parameters to iterate through different settings to determine the robustness of the solution.

Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.

Abstract: A circuit includes a plurality of series-coupled delay buffers and a plurality of logic gates. Each logic gate includes first and second inputs. The first input of each logic gate is coupled to a corresponding one of the delay buffers. The circuit also includes a plurality of flip-flops. Each flip-flop includes a data input and a data output. The data input is coupled to an output of a corresponding one of the logic gates and the data output is coupled to the second input of one of the corresponding logic gates.

Abstract: According to an embodiment, a bipolar transistor is disclosed for Electrostatic discharge (ESD) management in integrated circuits. The bipolar transistor enables vertical current flow in a bipolar transistor cell configured for ESD protection. The bipolar transistor includes a selectively embedded P-type floating buried layer (PBL). The floating P-region is added in a standard NPN cell. During an ESD event, the base of the bipolar transistor extends to the floating P-region with a very small amount of current. The PBL layer can provide more holes to support the current resulting in decreased holding voltage of the bipolar transistor. With the selective addition of floating P-region, the current scalability of the bipolar transistor at longer pulse widths can be significantly improved.

Abstract: A voltage regulator and a gate control circuit for an aid transistor coupled to assist a pass element for the voltage regulator during line transients having a given slope are disclosed. The gate control circuit includes a first circuit coupled to receive an output voltage of the voltage regulator on a first node and to provide a gate control voltage that mirrors the output voltage on a second node. A low pass filter is coupled to receive the gate control voltage and to provide a filtered gate control voltage to the gate of the aid transistor.

Abstract: An integrated circuit (IC) package includes a first leadframe having a top surface and a bottom surface. An IC die has an active side coupled to the first leadframe bottom surface and has a back side. A second leadframe has a top surface and a bottom surface. The back side of said IC chip is coupled to the top surface of the second leadframe.

Abstract: A method for ultrasound based heart rate detection in a heart rate monitoring system is provided that includes receiving a demodulated Doppler ultrasound signal, applying a bandpass filter to the demodulated Doppler ultrasound signal to remove a direct current (DC) component and out-of-band noise, wherein a filtered demodulated Doppler ultrasound signal is generated, rectifying the filtered demodulated Doppler ultrasound signal to generate a rectified filtered demodulated Doppler ultrasound signal, applying a low-pass filter to the rectified filtered demodulated Doppler ultrasound signal to filter out undesired components to leave a resulting signal corresponding to power shift due to heart rate, detecting peaks in the resulting signal, and computing a heart rate based on the detected peaks.

Abstract: Apparatus providing an integrated transformer are disclosed. An example apparatus includes a power conversion system including a switching circuit including a first primary side transistor coupled between a first input node and a switching node, and a second primary side transistor coupled between the switching node and a second input node, a series circuit including a transformer primary winding, a capacitor, and an inductor coupled in series between the switching node and the second input node, a transformer secondary circuit including a first transformer secondary winding and a second transformer secondary winding, the first and the second transformer secondary windings electrically between a first converter output and a second converter output, the transformer primary winding and the transformer secondary windings wound around at least a portion of a corresponding one of a transformer core in an infinity winding arrangement.

Abstract: At least some embodiments are directed to a receiver system that comprises a first oscillation module configured to provide oscillating signals of differing frequencies and a second oscillation module configured to provide other oscillating signals of the differing frequencies. The second oscillation module is configured to produce less noise than the first oscillation module. A controller is coupled to the first and second oscillation modules and configured to selectively activate and deactivate each of the first and second oscillation modules based on signal strengths of primary signals received via a wireless medium and based on signal strengths of interference signals received via the wireless medium.

Abstract: Methods, apparatus, systems and articles of manufacture to control injection for frequency response measurement. An example method includes calculating a gain of a circuit. The gain is calculated based on a measured response of the circuit to a first disturbance injected at a first frequency. A second frequency at which a second disturbance is to be injected into the circuit is identified. An amplitude at which the second disturbance is to be injected into the circuit at the second frequency is calculated. The amplitude calculated based on a measurement noise and the gain of the circuit at the first frequency. The second disturbance is injected into the circuit using the second frequency and the amplitude.

Abstract: A chip scale vapor cell and millimeter wave atomic clock apparatus are disclosed. The chip scale vapor cell includes a first substrate and a second substrate bonded to the first substrate with a bonding material. A primary hermetic cavity includes a first bottom wall and first sidewalls formed in the first substrate and a first top wall formed by the lower surface of the second substrate. A secondary hermetic cavity includes a second bottom wall and second sidewalls formed in the first substrate and a second top wall formed by the lower surface of the second substrate. The secondary hermetic cavity is separate from the primary hermetic cavity and surrounds the perimeter of the primary hermetic cavity. A gas, which can be a dipolar molecular gas, is sealed in the primary hermetic cavity and the secondary hermetic cavity at a given initial pressure.

Abstract: Disclosed examples provide wafer-level integration of magnetoresistive sensors and Hall-effect sensors in a single integrated circuit, in which one or more vertical and/or horizontal Hall sensors are formed on or in a substrate along with transistors and other circuitry, and a magnetoresistive sensor circuit is formed in the IC metallization structure.

Abstract: A lever shifter includes an output driver and a high-side gate driver. The high-side gate driver is configured to drive the high-side output transistor, and is coupled to an on pulse signal line that conducts an on pulse, and is coupled to an off pulse signal line that conducts an off pulse. The high-side gate driver includes a blocking circuit configured to enable generation of a drive signal to the high-side output transistor based on a voltage of a first of the on or off pulse signal line being greater than a first predetermined amount and a voltage of a second of the on or off signal line being less than a second predetermined amount.

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

Abstract: An active electromagnetic interference (EMI) filter includes an amplifier configured to sense noise signals on a power conductor, and drive a cancellation signal onto the power conductor. The cancellation signal is to reduce the amplitude of the noise signals. Some embodiments of the active EMI filter include a high frequency compensation network that improves the high frequency phase margin of the active EMI filter and improves the stability of the active EMI filter at high frequencies. Some embodiments of the active EMI filter include a low frequency compensation capacitor that increases the phase margin of the active EMI filter at low frequencies. Some embodiments of the active EMI filter include low frequency compensation circuitry that increases the low frequency tolerance of the active EMI filter.

Abstract: A sound recognition system including time-dependent analog filtered feature extraction and sequencing. An analog front end (AFE) in the system receives input analog signals, such as signals representing an audio input to a microphone. Features in the input signal are extracted, by measuring such attributes as zero crossing events and total energy in filtered versions of the signal with different frequency characteristics at different times during the audio event. In one embodiment, a tunable analog filter is controlled to change its frequency characteristics at different times during the event. In another embodiment, multiple analog filters with different filter characteristics filter the input signal in parallel, and signal features are extracted from each filtered signal; a multiplexer selects the desired features at different times during the event.

Abstract: A method, receiver and system for isolated wireless data transfer are disclosed. The receiver includes a switching mixer connected to receive a data signal and a local oscillator signal and to output a mixed differential signal, a programmable gain amplifier using an operational transconductance amplifier (OTA) and resistive feedback, the OTA connected to receive the mixed differential signal and to provide an amplified differential signal to a polyphase filter, and an analog demodulator to demodulate the output of the polyphase filter and provide digital output.

Abstract: In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

Abstract: Disclosed examples include integrated circuits, fabrication methods and ESD protection circuits to selectively conduct current between a protected node and a reference node during an ESD event, including a protection transistor, a first diode and a resistor formed in a first region of a semiconductor structure, and a second diode formed in a second region isolated from the first region by a polysilicon filled deep trench, where the first and second diodes include cathodes formed by deep N wells alongside the deep trench in the respective first and second regions to use integrated deep trench diode rings to set the ESD protection trigger voltage and prevent a parasitic deep N well/P buried layer junction from breakdown at lower than the rated voltage of the host circuitry.

Abstract: An electrostatic discharge (ESD) logging system includes ESD detection circuitry having at least one input electrically connected coupled to a node of an ESD protection circuit. The ESD detection circuitry provides a detector signal in response to detecting an ESD event at the node of the ESD protection circuit. Capture circuitry is electrically connected to an output of the ESD event detector. The capture circuitry asserts a capture signal to indicate the occurrence of the ESD event in response to the detector signal. A logic circuit provides a logic output in response to the capture signal.