Abstract: A controller is configured to perform self-calibration to maintain approximately a desired switching frequency of a power converter. The self-calibration performed by the controller at least partially mitigates detrimental effects associated with variation in an actual switching frequency of the power converter from a designed switching frequency. The controller maintains approximately the desired switching frequency, in one example, in view of a delay inherent in the control by the controller of the power converter.

Abstract: Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.

Abstract: An embodiment of the invention provides a method for changing a multi-processor system from a performance mode to a safety mode while the system continues to run software. When an external event or exception occurs, context is switched from the performance mode to the safety mode. After context is switched, at least one pair of CPUs is synchronized to operate in the safety mode. In addition, a multi-processor system may be switched form the safety mode to the performance mode while the software continues to operate.

Abstract: Apparatus, devices, and systems to provide a low quiescent current load switch are disclosed. A disclosed load switch circuit includes a transconductor to convert a voltage to a current input to a transistor gate, the current input to the transistor gate to control the gate to deliver power to a load from a power supply. The example circuit includes a resistor to provide power from a charge pump to the gate as controlled by the transconductor. A disclosed apparatus includes a driver to control a gate of a transistor, the gate to enable the transistor to deliver power to a load from a power supply when the gate is activated, and a gate slope control to control a rate of change over time of a voltage associated with the gate to activate the gate and to disable the driver when the gate is activated.

Abstract: Methods and apparatus providing a vertically constructed, temperature sensing resistor are disclosed. An example apparatus includes a semiconductor substrate including a first doped region, a second doped region, and a third doped region between the first and second doped regions, the third doped region including a temperature sensitive semiconductor material; a first contact coupled to the first doped region; a second contact opposite the first contact coupled to the second doped region; and an isolation trench to circumscribe the third doped region.

Abstract: A method to improve transistor performance uses a wafer (100) of single-crystalline semiconductor with a first zone (102) of field effect transistors (FETs) and circuitry at the wafer surface, and an infrared (IR) laser with a lens for focusing the IR light to a second depth (112) farther from the wafer surface than the first depth of the first zone. The focused laser beam is moved parallel to the surface across the wafer to cause local multi-photon absorption at the second depth for transforming the single-crystalline semiconductor into a second zone (111) of polycrystalline semiconductor with high density of dislocations. The second zone has a height and lateral extensions, and permanently stresses the single-crystalline bulk semiconductor; the stress increases the majority carrier mobility in the channel of the FETs, improving the transistor performance.

Abstract: Disclosed examples include isolated dual active bridge (DAB) DC to DC converters with first and second bridge circuits, a transformer with a sense coil, and a secondary side control circuit to provide secondary side switching control signals to regulate an output voltage or current signal by controlling a phase shift angle between switching transitions of the secondary side switching control signals and switching transitions of a secondary side clock signal, where the secondary side control circuit includes a clock recovery circuit to synchronize the secondary side clock signal to transitions in a sense coil voltage signal of the sense coil.

Abstract: A GNSS receiver to track low power GNSS satellite signals. The GNSS receiver includes a frequency locked loop (FLL) that measures a current doppler frequency of the satellite signal. A delay locked loop (DLL) measures a current code phase delay of the satellite signal. A current operating point corresponds to the current doppler frequency and the current code phase delay of the satellite signal. A grid monitor receives the satellite signal and the current operating point, and measures a satellite signal strength at a plurality of predefined offset points from the current operating point. The FLL and the DLL are centered at the current operating point. A peak detector is coupled to the grid monitor and processes the satellite signal strengths at the plurality of predefined offset points and re-centers the FLL and the DLL to a predefined offset point with the satellite signal strength above a predefined threshold.

Abstract: A method for evaluating a leadframe surface includes positioning a leadframe on a measurement apparatus at a first predetermined distance relative to an end portion of a light source of an optical sensor; irradiating a predetermined area on a surface of the leadframe with light having a single predetermined wavelength from the light source; receiving, with a light receiver of the optical sensor, reflected light from the predetermined area on the surface of the leadframe, and converting the reflected light into an electric signal; determining a reflection intensity value of the predetermined area on the surface of the leadframe based on the electric signal; and calculating a reflection ratio of the predetermined area on the surface of the leadframe based on the reflection intensity value and a predetermined reference reflection intensity value associated with the light source.

Abstract: A circuit includes an input stage that includes a first transistor device configured to generate a first output signal in response to a first bias current activating the first transistor device by exceeding a first threshold voltage of the first transistor device. A compensation stage includes a second transistor device coupled with a third transistor device. The second transistor device is activated in response to the first output signal exceeding a second threshold voltage of the second transistor device. The third transistor device is activated in response to activation of the second transistor device and a second bias current. The compensation stage is configured to generate a second output signal in response to the activation of the third transistor device. An output stage is configured to generate a reset signal in response to the second output signal exceeding a third threshold voltage.

Abstract: A system includes a storage capacitor coupled between an input voltage source and a ground terminal, a voltage sensing circuit coupled to the input voltage source and to the storage capacitor, a first transistor coupled to the voltage sensing circuit, a current mirror circuit coupled to the first transistor, a diode coupled between the storage capacitor and the current mirror circuit, and a second transistor configured to couple between a gate of a power switching device and the ground terminal. A gate of the second transistor is coupled to the storage capacitor by way of the voltage sensing circuit.

Abstract: One example includes a transconductor system. The system includes a first transconductance amplifier that generates a control current in response to a first input voltage. The system also includes a second transconductance amplifier that generates an output signal in response to a second input voltage. The system further includes an intermediate amplifier that generates a control voltage in response to the control current and a third input voltage. The control voltage can be provided to the first and second transconductance amplifiers to set a transconductance of each of the first and second transconductance amplifiers to be approximately equal.

Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

Abstract: A control unit device in one disclosed embodiment includes a receiver and a memory that stores one or more operation keys and program instructions. The control unit further includes a processor coupled to the receiver and the memory. The program instructions are executable by the processor to cause the control unit device to, in response to a revocation command received by the receiver, perform a revocation process by selecting which of the one or more operation keys to retain in the memory based on, for each of the one or more operation keys, whether the control unit receives a message encrypted by the operation key during the revocation process.

Abstract: A method of operating a wireless communication system is disclosed (FIG. 6). The method includes receiving a virtual cell identification (VCID) parameter (600) from a remote transmitter. A base sequence index (BSI) and a cyclic shift hopping (CSH) parameter (604,606) are determined in response to the VCID. A pseudo-random sequence is selected in response to the BSI and CSH (610,612). A reference signal is generated using the selected pseudo-random sequence (614).

Abstract: A multiphase DC-DC converter includes a first phase circuit including a higher inductance inductor and a second phase circuit including a lower inductance inductor. An output of the inductors are tied together providing a Vout. A phase manager and current sharing (PMCS) block receives a feedback signal from a feedback network coupled between Vout and the PMCS block that receives current feedback from phase circuits. The PMCS block generates driver control signals at a first time when a load is requesting a lower load current for controlling the phase circuits to operate with a first current sharing ratio to provide the lower load current, and at a second time when the load is requesting a higher load current controls the phase circuits to operate at a second current sharing ratio that is different from the first current sharing ratio having a higher average second phase circuit current.

Abstract: In a Power over Ethernet (PoE) system, a Powered Device (PD) having circuitry to measure the load current from a Power Sourcing Equipment (PSE) in the PD. Circuitry compares the measured load current with a first threshold. Circuitry automatically generates load pulses for signaling the PSE. The pulse widths of the load pulses are measured and the widths are automatically adjusted, that power to the PD should be maintained.

Abstract: In described examples, a hermetic package of a microelectromechanical system (MEMS) structure includes a substrate having a surface with a MEMS structure of a first height. The substrate is hermetically sealed to a cap forming a cavity over the MEMS structure. The cap is attached to the substrate surface by a vertical stack of metal layers adhering to the substrate surface and to the cap. The stack has a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance. The stack has: a first bottom metal seed film adhering to the substrate and a second bottom metal seed film adhering to the first bottom metal seed film; and a first top metal seed film adhering to the cap and a second top metal seed film adhering to the first top metal seed film.

Abstract: A wireless transmitter for transmitting bits to a wireless receiver. The wireless transmitter comprises: (i) circuitry for generating binary data bits; and (ii) circuitry for providing a first spreading sequence for a first bit in the binary data bits and for providing a second spreading sequence for a second bit in the binary data bits, wherein the second bit is complementary to the first bit. Each spreading sequence consists of an integer number N of bits, and the circuitry for providing provides a same bit value in an integer number M of bit positions in the first and second spreading sequences, where M<N.

Abstract: In some examples, an amplifier stage includes a voltage-gain amplifier stage and a negative capacitance circuit coupled to the voltage-gain amplifier stage, the negative capacitance circuit comprising a first transistor that provides a first temperature-biased current.