Abstract: In a power converter, a circuit determines an average value of an inaccessible current from an average value of an accessible current and a value of the operating duty cycle of the converter. A method of measuring an average value of an inaccessible current from a measured value of a current, in a power converter, by a duty cycle of a pulse width modulation (PWM) signal, representing a duty cycle of the power converter. Coupling a voltage representing the measured value to an input of a low pass filter during a time period (D) and coupling the input of the low pass filter to a reference voltage during a time period (1?D).

Abstract: An integrated fault-tolerant augmented area viewing system includes, for example, a subsystem processor for receiving a safety signal for blind spot monitoring from a blind spot sensor and for generating a subsystem processor video output signal in response to the received safety signal. Selector circuitry selects the subsystem processor video output signal or a master controller video output signal received from a master controller and generates a selected video output signal in response. The selector circuitry performs the selection of the video output signal selection in response to receiving a safety request signal generated in response to a user action. A buffer outputs the selected video output signal for displaying on a display for viewing by the user.

Abstract: A control processor for a video encode-decode engine is provided that includes an instruction pipeline. The instruction pipeline includes an instruction fetch stage coupled to an instruction memory to fetch instructions, an instruction decoding stage coupled to the instruction fetch stage to receive the fetched instructions, and an execution stage coupled to the instruction decoding stage to receive and execute decoded instructions. The instruction decoding stage and the instruction execution stage are configured to decode and execute a set of instructions in an instruction set of the control processor that are designed specifically for accelerating video sequence encoding and encoded video bit stream decoding.

Abstract: Disclosed techniques relate to forming a block sum of picture elements employing a vector dot product instruction to sum packed picture elements and the mask producing a vector of masked horizontal picture element. The block sum is formed from plural horizontal sums via vector single instruction multiple data (SIMD) addition.

Abstract: A driver circuit includes a first termination resistor and a distributed amplifier comprising a plurality of pairs of input transistors and comprising inductors coupled between each pair of input transistors. The driver circuit also includes a distributed current-mode level shifter coupled to the first termination resistor. The distributed current-mode level shifter includes a first plurality of inductors coupled in series between the first termination resistor and the distributed amplifier and a first plurality of capacitive devices. Each capacitive device is coupled to a power supply node and to a node interconnecting two of the series-coupled inductors.

Abstract: A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.

Abstract: In some examples, an apparatus includes a plurality of first transistors coupled to a first input terminal and a first output terminal. The apparatus also includes a plurality of second transistors coupled to a second input terminal and a second output terminal. The apparatus further includes a plurality of first dummy transistors coupled to the first input terminal and the second output terminal. The apparatus also includes a plurality of second dummy transistors coupled to the second input terminal and the first output terminal.

Abstract: A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

Abstract: A system includes a class D amplifier and a current steering digital-to-analog converter (DAC) directly connected to the class D amplifier. The system also includes a common mode servo circuit coupled to a node interconnecting the current steering DAC to the class D amplifier. The common servo circuit amplifies a difference between a common mode signal determined from the node and a reference voltage and generates a feedback current to the node based on the amplified difference. A feed-forward common-mode compensation circuit is included to reduce an alternating current (AC) ripple from the class D amplifier. The feed-forward common-mode compensation circuit includes first and second resistors coupled to respective outputs of the class D amplifier. A current mirror is coupled to the first and second resistors and is configured to sink a current from the node to ground that approximates a common mode feedback current of the class D amplifier.

Abstract: A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a near field communication (NFC) coupler located on the substrate. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a field confiner located between the NFC coupler and the port region on the housing configured to guide electromagnetic energy emanated from the NFC coupler through the port region to a port region of an adjacent module. An artificial magnetic conductor surface is positioned adjacent the backside of each NFC coupler to reflect back side electromagnetic energy with a phase shift of approximately zero degrees.

Abstract: A zero-IF transceiver includes a Rx having an IQ receiver path with a digital portion including a modem and a down-converter, and a Tx having an IQ transmit path with a digital portion including a modem for generating a complex and substantially balanced time-domain signal, an IQMM correction block, and an up-converter. An IQMM estimation block is coupled between time-domain parts of the Rx and the Tx modems. The IQMM estimation block is coupled to an input of the IQMM correction block. A loopback path couples the time-domain signal from the Tx to the Rx. The IQMM estimation block receives a first time-domain signal from the Rx modem and the time-domain signal before the IQMM correction block, and estimates in a digital time-domain an IMage Rejection Ratio (IMRR) of the Tx(?). The IQMM correction block is for correcting the IQMM to provide an IQ corrected OFDM signal using the ?.

Abstract: A multilayer butterfly network is shown that is operable to transform and align a plurality of fields from an input to an output data stream. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits. This invention used precalculated inputs and simple combinatorial logic to generate control signals for the butterfly network. Controls are independent for each layer and therefore are dependent only on the input and output patterns. Controls for the layers can be calculated in parallel.

Abstract: A method of certifying uniform distribution of mechanical pressure comprises an apparatus for moving an object, the apparatus including an arm (410) with a joint (430) for adjusting a fixture (420) having a flat surface area (420a). The fixture includes vacuum suction for holding the object. The method further uses a pressure sensor (450) with a flat surface area (450a), displaying output voltage as a function of mechanical pressure applied. When the sensor is placed on a chuck with vacuum suction, the apparatus moves (460) to bring the flat fixture surface in touch with the flat sensor. Mechanical pressure is applied from the fixture to the sensor; the voltage output of the sensor is monitored to certify uniform distribution of the fixture pressure across the sensor area.

Abstract: Methods and apparatus to calibrate micro-electromechanical systems are disclosed. An example pressure sensor calibration apparatus includes a mechanical lift to move a pressure sensor between a first height, a second height, and a third height; one or more sensors to measure first pressure and capacitance values at the first height, second pressure and capacitance values at the second height, and third pressure and capacitance values obtained at the third height; and a calibrator to determine calibration coefficient values to calibrate the pressure sensor based on the first pressure and capacitance values obtained at the first height, the second pressure and capacitance values at the second height, and the third pressure and capacitance values obtained at the third height.

Abstract: A backgrind (BG) tape includes an adhesive material having a thinner tape region with a first thickness having an area sized to accommodate a substrate therein including an active semiconductor top side surface including a plurality of chips each including at least one transistor and at least one metallization level with bond pads connected to nodes of the transistor and bumps on or coupled to the bond pads. The BG tape also includes a thicker tape region along at least a periphery of the BG tape having a second thickness that is greater than the first thickness.

Abstract: In some embodiments, a semiconductor wafer testing system comprises a first plate configured to couple to a probe head, the first plate including a first alignment feature, a biasing member, a stopper, and pins. The system also comprises a second plate configured to fasten to the first plate and including a second alignment feature configured to engage with the first alignment feature. The first and second alignment features are configured to align the pins with a test wafer positioned between the first and second plates. The biasing member and the stopper are configured to cooperate to regulate a pressure with which the test wafer contacts the pins when the second plate is fastened to the first plate.

Abstract: A sort buffer includes a phase sector determination circuit, a phase sector update circuit, and a phase sector completion circuit. The phase sector determination circuit is configured to determine a phase sector corresponding to a phase of a first sine and cosine sample pair received from an encoder or resolver. The phase sector update circuit is configured to determine whether a second sine and cosine sample pair corresponding to the phase sector is stored in a lookup table (LUT) and, in response to a determination that a second sine and cosine sample pair corresponding to the phase sector is not stored in the LUT, store the first sine and cosine sample pair in the LUT. The phase sector completion circuit is configured to determine whether the LUT has stored, for each of a plurality of phase sectors, a corresponding sine and cosine sample pair.

Abstract: The disclosure provides a circuit that includes an analog control block, and a plurality of temperature sensors coupled to the analog control block. At least one temperature sensor of the plurality of temperature sensors includes a first transistor coupled to a first current source. A second transistor is coupled to a second current source and to the first transistor. The analog control block measures a local temperature from a first potential generated across the first transistor and from a second potential generated across the second transistor.

Abstract: Disclosed examples include redundant Power over Ethernet (PoE) systems, powered device (PD) controllers and methods in which a first PD controller sends a signal to indicate to the other PD controllers that the first PD controller is powered, and a second PD controller newly connected or reconnected to a corresponding power sourcing equipment (PSE) refrains from turning off a shared DC-DC converter, and the second PD controller waits to allow an inrush current delay of the corresponding PSE to complete before allowing current flow between the DC-DC converter and the corresponding PSE, and the second PD controller selectively provides a signal to request an application circuit powered by the DC-DC converter to temporarily reduce its power consumption below a predetermined value if the corresponding PSE is configured to provide no more than the predetermined value of power.

Abstract: A method of controlling an electric motor (motor) includes providing a processor having an associated memory storing a stator resistance (Rs) estimation (RSE) algorithm that is programmed to implement the RSE algorithm to execute steps including injecting a current waveform at an arbitrary frame of reference into the stator using a field-oriented-control (FOC) motor controller including an Id controller and an Iq controller, and measuring current and voltage values from the motor responsive to the injecting. The measured current and voltage values are then transformed into transformed current and voltage values in a d/q coordinate system. The transformed current and voltage values are low pass filtered to generate filtered d/q current and voltage values, and a value for Rs is estimated from the filtered d/q current and voltage values. The arbitrary frame of reference can be a time-varying frame of reference.