Abstract: The invention provides systems, devices, and methods for frequency hopping. In one method embodiment, the invention hops between frequencies by using the same channel to transmit data from a master to a slave, and from the slave to the master. One system embodiment provides an enhanced master coupled to an enhanced slave. In one device embodiment, the invention is a computer readable medium adapted to enable frequency hopping in a frequency band.

Abstract: In accordance with an embodiment of the invention, there is a method of designing a lithography mask. The method can comprise determining a maximum width of a shifter, wherein the maximum width corresponds to a width of a shifter for a first set of features and determining whether the shifter having the maximum width can be placed in a shifter space for a second set of features. The method can also comprise incrementally decreasing the width of the shifter to be placed into the shifter space for the second set of features when the shifter having the maximum width cannot be placed in the shifter space for a feature in the second set of features until an acceptable shifter width can be determined or until the shifter width is reduced to a predetermined minimum shifter width.

Abstract: One embodiment of the present invention includes a column multiplexer for accessing data from a memory array comprising an output node having a logic state that is based on a logic state of a control node, and column elements, each comprising a first pair of series connected switches controlled by a column select signal and a bit line signal associated with data stored in a plurality of memory cells. The first pair of switches is configured to set the control node to a logic low state based on a logic state of the bit line signal. The column elements each also comprise a second pair of series connected switches controlled by the bit line signal and a complement of the column select signal. The second pair of switches is configured to set the control node to a logic high state based on the logic state of the bit line signal.

Abstract: One aspect of the invention provides a method of manufacturing a FeRAM semiconductor device having reduce single bit fails. This aspect includes forming an electrical contact within a dielectric layer located over a semiconductor substrate and forming a first barrier layer over the dielectric layer and the electrical contact. The first barrier layer is formed by depositing multiple barrier layers and densifying each of the barrier layers after its deposition. This forms a stack of multiple barrier layers of a same elemental composition. The method further includes forming a second barrier layer over the first barrier layer and forming a lower capacitor electrode, a ferroelectric dielectric layer over the lower capacitor, and forming an upper capacitor electrode over the ferroelectric dielectric layer. A device made by this method is also provided herein.

Abstract: One embodiment of the invention includes a digital-to-analog converter (DAC) circuit. The DAC circuit includes a DAC portion configured to generate an output voltage having a magnitude that varies based on a plurality of digital values of a digital input signal. The DAC circuit also includes a test portion configured to compare the output voltage with a predetermined test voltage for each of the plurality of digital values of the digital input signal during a test mode. The test portion can provide a digital output signal corresponding to one of acceptance and failure of the DAC circuit.

Abstract: Overcurrent and overload protection for the power output of a pulse-width-modulated digital audio system is disclosed. The overcurrent protection circuitry includes a latch that is set in responsive to output current from the power output stage that exceeds an overcurrent threshold; the output of the latch gates the pulse-width-modulated control signal to block power output for the remainder of the current pulse-width-modulated cycle; upon the end of the cycle, or the beginning of the next, the latch is cleared to enable power output in that next cycle. Overload protection is provided by circuitry including counters for counting the relative number of overcurrent cycles to normal, non-overcurrent cycles, and generating an overload signal to block power output in the event of too frequent overcurrent cycles.

Abstract: The present disclosure describes methods and systems for secure debugging and profiling of a computer system. Some illustrative embodiments may include a system including a processor with a first processing stage and a first attribute register associated with the first processing stage, and including a memory system coupled to the processor. An instruction and an attribute value are stored within the memory system, wherein the instruction is loaded into the first processing stage and the attribute value is loaded into the first attribute register. Export of debug and profiling data from the first processing stage is disabled if the attribute value in the first attribute register indicates that the instruction in the first processing stage is a secure instruction, and further indicates that secure emulation is disabled.

Abstract: An overcurrent protection system and method are disclosed. In one embodiment the overcurrent protection system includes a first switch connected between a supply voltage and an output voltage. A comparator circuit provides a comparator output signal having first and second values that depend on a comparison of the output voltage relative to the supply voltage, the first value indicating an overcurrent condition. A control circuit is coupled to provide a control signal to a control node of the first switch for controlling the first switch in one of first and second operating modes according to the value of the comparator output signal. The control circuit controls the first switch in the first mode to limit the current through the first switch to a level between predetermined upper and lower current levels in response to the comparator output signal having the first value.

Abstract: Methods and devices are disclosed for cleaning contactors equipped with contact pins such as pogo pins include steps which may be performed in concert with common semiconductor device testing processes using automatic test equipment and associated handlers. The preferred embodiments of the invention include method steps for mounting a surrogate cleaning device in a tester load board socket and applying the contact pins associated with automatic test equipment to the surrogate cleaning device for cleaning.

Abstract: A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions.

Abstract: A method of fabricating graphene transistors, comprising providing an SOI substrate, performing an optional threshold implant on the SOI substrate, forming an upper silicon layer mesa island, carbonizing the silicon layer into SiC utilizing a gaseous source, converting the SiC into graphene, forming source/drain regions on opposite longitudinal ends of the graphene, forming gate oxide between the source/drain regions on the graphene, forming gate material over the gate oxide, creating a transistor edge, depositing dielectric onto the transistor edge and performing back end processing.

Abstract: One embodiment of the present invention includes a method for synchronizing packet production and receipt from a digital signal processor (DSP) with polled transmission opportunities in an IEEE 802.11e network. The method comprises producing a packet via the DSP and transmitting the packet from the DSP to a transmission device at a time that is substantially synchronized with a next polled transmission opportunity granted by an access point in an IEEE 802.11(e) network. The method also comprises time stamping the arrival of the packet at the transmission device and transmitting the packet from the transmission device.

Abstract: A method for detecting defects during semiconductor device processing can include providing a substrate having a semiconductor comprising layer with electrically isolated application and test circuits are formed thereon, directing an electron current inducing beam to the test circuit; measuring a current between the first and the second contact pads in the test circuit; determining an electron beam induced current (EBIC); and identifying one or more defect locations in the test circuit based on the EBIC and a location of the electron beam corresponding to the EBIC. A test circuit can include a plurality of semiconductor devices connected in parallel, a first contact pad coupled to a first terminal of the semiconductor devices, and at least a second contact pad coupled to a substrate terminal associated with the semiconductor devices.

Abstract: System and methods for a digital linearization of a non linear element. Digital predistortion methods and circuitry for linearizing a non-linear element that address long or “memory” effects and shorter duration effects, these two predistortion functions are operated together in an adaptive fashion with the non-linear element to provide a highly linear system. A short duration predistortion block comprises an Nth order polynomial filter coupled to a programmable linear equalizer. The Nth order filter includes programmable non-linearities and variable delay taps. The Nth order filter may be configured to implement a non-sequential or a sequential ordered polynomial. The equalizer may, in a preferred embodiment, include circuitry for equalizing imbalances between real and complex signal values. The Nth order filter may implement a compound Volterra filter. The combined system of the predistortion circuitry and a non-linear element has a linear input-output signal response.

Abstract: An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.

Abstract: A wafer transfer machine transfers wafers from either of a first wafer cassette (55) and a second wafer cassette (56) having incompatible registration features into the other, and includes a support plate (30) having a top surface (38) for supporting the first and second wafer cassette. A first and second registration bosses attached to the top surface extend upward into registration features of the first and second wafer cassette, respectively. A carriage (1) is supported by and movable in opposite directions along a track mechanism (41A,B) that is attached in fixed relationship to the support plate (30). First and second wafer pushing members (10A,B) are supported by the carriage. Each wafer pushing member can be moved to push wafers in one of the wafer cassettes into the other by moving the carriage in one direction or the other.

Abstract: A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions.

Abstract: A method and apparatus for highlight detection. The method includes retrieving audio and video data, detecting a high audio energy scene of the retrieved audio data, detecting a key-line scene relevant to the high audio scene of the retrieved video data, detecting an in-play scene according to the key-line, and optimizing start and end point of the highlight scene.

Abstract: A semiconductor chip (102) assembled on a substrate (101). The substrate has a first surface (101a) including conductive traces (110), which have a first length (111) and a first width (112), the first width being uniform along the first length, and further a pitch (114) to respective adjacent traces. The semiconductor chip has a second surface (102a) including contact pads (121); the second surface faces the first surface spaced apart by a gap (130). A conductive pillar (140) contacts each contact pad; the pillar includes a metal core (141) and a solder body (142), which connects the core to the respective trace across the gap. The pillar core (141) has an oblong cross section of a second width (151) and a second length (152) greater than the second width. Trace pitch (141) is equal to or smaller than twice the second width (151). The trace pitch is equal to or smaller than the second length (152).

Abstract: A discontinuous conduction mode (DCM) converter is provided. The converter comprises a transformer having a primary and a secondary side, an RCD network, a rectifier, a switch, and a controller. The transformer has primary side with a first primary winding and a second primary winding and has a secondary side with a secondary winding. The RCD network is coupled to the first primary winding and is adapted to receive energy from the leakage inductance of the first primary winding. The rectifier is coupled to the second primary winding. The switch is coupled between the RCD network and ground. The controller receives indicia of a rectified voltage from the rectifier, indicia of current from the switch, indicia of transformer magnetization and controls the actuation of the switch. Preferably, the controller provides an actuation signal to the switch with actuation periods that are separated from one another by an interval that allows energy within the transformer to substantially dissipate.