Abstract: This invention is a digital television receiver receiving alternative broadcasts. Separate tuners receive separate broadcast signals, such as 12-segment HDTV and 1-segment QVGA. A multiplexer selects one tuner based upon receiver status of a first tuner. The selected signal is decoded and resized for a display. The decoder uses a frame buffer of images in the resized size. In the preferred embodiment the input signals are a 12-segment HDTV broadcast and a 1-segment QVGA broadcast and the resized size is VGA.

Abstract: This invention measures the propagation delay ?1 between the user equipment and a first cooperating unit and the propagation delay ?2 between the user equipment and a second cooperating unit. These propagation delays are used to compute a timing advance amount to the user equipment to enable coordinated multi-point reception. In a first embodiment one cooperating unit receives a function of the propagation delay, computes the timing advance amount and transmits a timing advance command to the user equipment. In a second embodiment a central unit performs these operations.

Abstract: Simulation of an electronic circuit including a model of a ferroelectric capacitor. The model of the ferroelectric capacitor includes a multi-domain ferroelectric capacitor, in which each of the domains is associated with a positive and a negative coercive voltage. A probability distribution function of positive and negative coercive voltages is defined, from which a weighting function of the distribution of domains having those coercive voltages is defined. The electrical behavior of the ferroelectric capacitor is evaluated by evaluating the polarization of each of the domains, as weighted by the weighting function. A time-dependent factor can be included in the polarization expression evaluated for each domain, to include the effect of relaxation. The effects of longer-term mechanisms, such as imprint, can be modeled by deriving a probability distribution function for the domains after an accelerated stress.

Abstract: This disclosure describes a processor system that allows non-real time code to execute normally, while permitting a real time interrupt in hardware or software to execute with minimal added latency.

Abstract: High speed networking systems such as PCI-Express and Serial Rapid I/O are based on the exchange of packets across switched networks of high speed serial links. Information in the headers of these packets indicate the kind of transaction they represent. Queuing all received packets in a single queue will cause interactions between transaction types. Indirection can be used create the effect of multiple independent queues from a shared memory. This provides efficient centralized packet storage, while allowing independent processing of different transactions types.

Abstract: A method and apparatus for wheelchair control. The position and distance of a touch point on a touch pad is used to set speed and wheel differential control. The two major wheels of the wheelchair are controlled according to these set quantities. Exceeding either of two horizontal accelerations measured by an accelerometer limits the set speed. Wheelchair control is shut down upon exceeding a vertical acceleration limit.

Abstract: This invention relates to multi-core, multi-processing, factory multi-core and DSP multi-core. The nature of the invention is related to more optimal uses of a multi-core system to maximize utilization of the processor cores and minimize power use. The novel and inventive steps are focused on use of interrupts and prioritized interrupts, along with optional in-built methods, to allow systems to run more efficiently and with less effort on the part of the programmer.

Abstract: A fully differential amplifier circuit provided according to an aspect of the present invention contains a stabilization block to measure the common mode component at the output of an input stage, and to inject a current proportionate to the common mode component into each of a pair of paths forming the output of the input stage to stabilize a feedback loop formed by the input stage, an output stage and a common mode feedback block. In an embodiment, the stabilization block contains a buffer to receive the measured common mode component and to provide a buffered output. The injected current is generated based on the buffered output. Due to the presence of the buffer, the differential loop may not be affected by injection of the additional current, thereby avoiding any distortions in the output signal.

Abstract: A method, system, and apparatus to a novel single supply level shifter circuit for multi-voltage designs, capable of up/down shifting are disclosed. In one embodiment, a system includes a first circuit, a second circuit, a voltage source with an output voltage equal to a voltage value of the second circuit, a level shifter circuit coupled with both an output of the first circuit and an output of the voltage source and wherein the level shifter circuit is used to convert a voltage value of a signal from the first circuit to the voltage value of the second circuit, and a capacitor loop circuit associated with the first circuit, the level shifter circuit and the voltage source and configured with a capacitor to charge from at least one of a first circuit output voltage.

Abstract: Disclosed herein is a micromirror device having a reflective mirror plate with reduced dimensions. The micromirror device can be a member of an array of micromirror devices for use in optical signal modulations, such as display applications and optical signal switching applications.

Abstract: A method of determining indicators for matrix codewords in a matrix codeword codebook, where the matrix codewords are adapted for communicating information between a transmitter and a receiver. The method includes providing a lookup table that is associated with multiple codewords that are associated with a codebook. The lookup table has m rows, and each row in the lookup table has a one-to-one correspondence with a codeword in the multiple codewords. Each row has p entries and each of the p entries holds a codeword indicator that identifies a codeword in the multiple codewords. The (i,j)th entry in the lookup table holds the codeword indicator identifying the jth most similar codeword to the codeword associated with the ith row according to a similarity metric, where 1?i?m and 1?j?p, and the m rows include a row k.

Abstract: A method and apparatus for determining electro-migration (EM) in integrated circuit designs is disclosed. In one embodiment, a method includes pre-characterizing an output current waveform for a logic cell of the circuit at selected load and input slew points, estimating an effective load and operating slews at a chip level of the circuit and directly generating an equivalent current source waveform at output, evaluating current densities through a metal segment of the circuit using a fast solver, parametrically representing process variations and a netlist to parametrically model the interconnect variations of the circuit, and determining current densities for selected yield numbers using a parametrically generated current source on an interconnect network, wherein calculated results statistically predict a point of current density less than 9?? a through any metal segment in the parametrically modeled circuit.

Abstract: One embodiment of an apparatus for filtering an electrical signal includes a loop filter with an input and an output that applies a transfer function to a signal at the input. The transfer function has substantially no real part. The loop filter has a dominant pole placed substantially at or above an upper frequency in the frequency range of interest for the loop filter.

Abstract: A novel schematic for executing search, write and valid bit clear operations in one cycle in a CAM system that includes a plurality of CAM blocks is disclosed. In one embodiment, the plurality of CAM blocks are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of CAM cells and associated read/write bit lines connecting the group of CAM cells to an addressed search circuit. The write operation depends on the output of the search operation, wherein the same data is written in to the CAM when the search operation results in a miss in a given cycle. Further, during the same cycle a valid bit clear operation is also performed. The resulting CAM cell provides a high speed three port operation.

Abstract: Systems, methods, and computer-readable media supporting thread abstraction in Java are provided. In some illustrative embodiments, a system is provided that includes a Java execution flow class that represents an execution flow context, an execution flow scheduler object including a Java native execution flow activation method, a Java virtual machine, a Java scheduler that executes on the Java virtual machine, and a Java thread class that extends the execution flow class. The execution flow class includes an execution flow execution method and a constructor that creates an execution flow context. The Java thread class includes an execution flow execution method that overrides the execution flow execution method of the execution flow class.

Abstract: An integrated circuit (IC), a method of testing an IC and a method of reading test results from an IC containing built-in self-test (BIST) circuitry. In one embodiment, the IC includes: (1) an external test bus interface, (2) read-write memory coupled to the external test bus interface, (3) other circuitry and (4) BIST circuitry, coupled to the external test bus interface, the read-write memory and the other circuitry and configured to test the read-write memory to identify a good data block therein, store in a predetermined data block in the read-write memory multiple instances of a pointer to the good data block, conduct a test of at least the other circuitry and store at least some results of the test in the good data block.

Abstract: A processor (1700) for processing instructions has a pipeline (1710, 1736, 1740) including a fetch stage (1710) and an execute stage (1870), a first storing circuit (aGHR 2130) associated with said fetch stage (1710) and operable to store a history of actual branches, and a second storing circuit (wGHR 2140) associated with said fetch stage (1710) and operable to store a pattern of predicted branches, said second storing circuit (wGHR 2140) coupled to said first storing circuit (aGHR 2130), said execute stage (1870) coupled back to said first storing circuit (aGHR 2130). Other processors, wireless communications devices, systems, circuits, devices, branch prediction processes and methods of operation, processes of manufacture, and articles of manufacture, as disclosed and claimed.

Abstract: An integrated circuit (IC) includes at least a first complementary MOS (CMOS) circuit, the first CMOS circuit comprising one or more first n-channel MOS (NMOS) transistors and one or more first p-channel MOS (PMOS) transistors, where the first NMOS transistors and the first PMOS transistors are arranged in the first CMOS circuit to drive at least a first common node of the first CMOS circuit. An average of the effective gate channel lengths of the first NMOS transistors (first NMOS average length) is at least 2% greater than an average of the effective gate channel lengths of the first PMOS transistors (first PMOS average length).

Abstract: Disclosed herein are a system and apparatus for operating a device that comprises an array of micromirrors. The system and apparatus are usable for repairing stuck micromirrors of the micromirror array during the operation. The reparation applies, at the ON state, two consecutive refresh voltages to the mirror plates of the micromirrors in the array with the pulses being separated in time longer than the characteristic oscillation time of the micromirrors. The reparation can be applied independently to the micromirrors. Alternatively, the reparation can be incorporated with a bias inversion process.

Abstract: In an embodiment, the invention provides a method for correcting soft errors in memory. A block of data is written in memory wherein all rows and all columns have a first checksum appended to it. A second checksum for each row and each column is generated after reading each row and each column from memory. The first and second checksum for each row and each column are compared for a compare such that when one and only one column has a miscompare, the logical value of any bit at an intersection of the one and only one column that has a miscompare and any row that has a miscompare is reversed.