Abstract: Ferroelectric memory devices and methods are provided, wherein a cell plateline signal is applied to a ferroelectric target cell capacitor and a zero cancellation capacitor is coupled with a bitline during a memory read operation. A negative pulse is applied to the zero cancellation capacitor during the cell plateline pulse to reduce the voltage on the bitline, thereby facilitating reduced cell plateline voltage levels while still allowing a high percentage of the ferroelectric saturation voltage to be applied across the ferroelectric cell capacitor.

Abstract: A micromechanical device having a deflectable member which contacts a stationary member. An antireflective coating is applied to portions of the micromechanical device to limit undesired reflection from the device. A passivation or lubrication layer is applied to the device to reduce stiction between the deflectable member and the stationary member. An insulator layer is utilized between the antireflective coating and the lubrication layer to prevent photoelectric-induced breakdown of the lubrication layer.

Abstract: A voltage feedback (“VF”) operational amplifier (“op-amp”) that includes a circuit operable to dynamically bias pre-driver transistors at the op amp output stage. This arrangement provides a dynamic bias from a common base gain stage (302) to the pre-drivers (338, 339) of the output stage (303) so that higher slew rate is achieved with minimal discontinuity in the signal.

Abstract: A test signal multiplexer receives supplies external test signals to a selected debug master central processing unit in a symmetrical multiprocessor system and debug slave signals to debug slave central processing units. An executive master test access port controller responds to the external test signals and controls the test signal multiplexer. A control register loadable via the executive master test access port stores the debug slave signals. A test data output multiplexer connects the test data output line of the selected debug master central processor unit to an external test data output line. The external test signals includes a debug state signal supplied to each central processing unit. This selects either a normal mode or a debug mode at each central processor unit.

Abstract: The objective of this invention is to provide a pulse signal generator with a simple constitution that can reduce the number of signals required for setting the pulse width, as well as a display device using said pulse signal generator. Pulse assignment signal DP0 input to the initial stage of pulse signal generating units PG(i,0)–PG(i,39) connected in cascade is sequentially transferred towards the last stage of the cascade connection. After transfer of the pulse assignment signal to the pulse signal generating unit in each stage, the count value of said pulse signal generating unit is initialized. Then, the pulses of pulse strings PS0–PS39 in the various pulse signal generating units are counted. The count value of the pulse string is compared to the pulse assignment signal in the comparison unit of each pulse signal generating unit, and, in accordance with the comparison result, the level of the drive pulse signal of the LED is inverted.

Abstract: A method of forming a gate electrode (24?) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (26), for example formed of silicon-rich nitride, is deposited over a polysilicon layer (24) from which the gate electrode (24?) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer (29) is then formed over the hardmask layer (26), and photoresist (30) is photolithographically patterned to define the pattern of the gate electrode (24?), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist (30) to the BARC layer (29). The remaining elements of the BARC layer (29) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer (26) by an anisotropic etch of that layer, using the trimmed BARC elements (29) as a mask.

Abstract: A method of reducing threshold voltage shift of a MOSFET transistor resulting after temperature and voltage stress, and an integrated circuit device fabricated according to the method. The method includes the steps of forming a nitrided dielectric layer on a semiconductor substrate, and subjecting the nitrided dielectric layer to an anneal at low pressure.

Abstract: In the present invention, a PMOS device comprises a channel region formed in {100} silicon with first and second source/drain region disposed on either side of the channel region. The channel region is oriented such that a current flow between the source/drain regions has a <100> direction through the channel region. Dielectric regions create a compressive stress on the channel region perpendicular to the current flow.

Abstract: The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).

Abstract: A method and circuit for facilitating control of the AC coupling for addressing input offset in an amplifier circuit are provided. In accordance with an exemplary embodiment, a control circuit comprises a pair of resistive networks coupled together through a capacitive coupling, with the pair of resistive networks configured between two amplifier devices of the amplifier circuit. The capacitive coupling is configured to prevent offset in the differences between input voltages to the two amplifier devices, and can comprise various types and configurations of capacitor networks, devices and components. The pair of resistive networks is configured to generate an output current signal from the two amplifier devices while facilitating a substantially identical capacitive loading on the two amplifier devices.

Abstract: A system comprising a ball grid array (“BGA”) substrate adapted to electrically couple to an application board using a plurality of solder balls, and a film adapted to abut the application board and the BGA substrate, the film comprising a plurality of perforations, the solder balls adapted to couple to the application board through the perforations.

Abstract: A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting plate.

Abstract: A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an address bus (the hash address generator converts a bus address present on the address bus into a current hashed address); a cache memory coupled to the address bus (the cache memory comprises a tag stored in one of a plurality of tag cache ways and data stored in one of a plurality of data cache ways); and a hash memory coupled to the address bus (the hash memory comprises a saved hashed address, the saved hashed address associated with the data and the tag). Less than all of the plurality of tag cache ways are enabled when the current hashed address matches the saved hashed addresses. An enabled tag cache way comprises the tag.

Abstract: A method, comprising immersing a package substrate used as part of a semiconductor device in a potassium iodide and iodine solution. The device comprises a substrate, a nickel layer abutting the substrate and comprising a black pad defect, and a gold layer abutting the nickel layer. The method also comprises rinsing the device with deionized water.

Abstract: The present disclosure describes a system and method for high performance, power efficient store buffer forwarding. Some illustrative embodiments may include a system, comprising: a processor coupled to an address bus; a cache memory that couples to the address bus and comprises cache data (the cache memory divided into a plurality of ways); and a store buffer that couples to the address bus, and comprises store buffer data, a store buffer way and a store buffer index. The processor selects the store buffer data for use by a data load operation if a selected way of the plurality of ways matches the store buffer way, and if at least part of the bus address matches the store buffer index.

Abstract: A system and method for multi-stage injection in a transfer molding system. Some exemplary embodiments may be a method used in a transfer molding system comprising compressing a molding compound, injecting a center portion of the compressed molding compound into a mold, and then injecting an outer portion of the compressed molding compound into the mold.

Abstract: A secure digital data distribution system (100) for preventing unauthorized access to digital data. The system utilizes an identification system module (116) embedded in a digital storage media (114) to grant authorization to media players (118). Prior to reading the digital data recorded on the media (114), an identification system interrogator (122) reads authorization data from the identification system module (116) to determine whether the media player (118) is authorized to read the media (114). If the authorization data matches the media player's unique identifier, authorization is granted and the media player (118) commences to read the media (114).

Abstract: The present invention provides, in one embodiment, a method (100) of forming dual work function metal gate electrodes in a semiconductor device. The method includes forming a gate dielectric (105) over a substrate (110) and depositing a mold layer (115) having a first opening (120) therein over the gate dielectric (105). The method further includes creating a first metal gate electrode (125) by depositing a first metal in the first opening (120). Other embodiments include an active device (200) produced by the above-described method and method of manufacturing an integrated circuit (300) using the above-described method.

Abstract: A transition between values of two successive bits is detected. The bit after the transition is used as one of the recovered bits. A recovery circuit may independently generate a sampling clock based on an analog signal, and sample the analog signal at time points specified by the sampling clock to generate multiple data bits. A multiplexor is used to provide a bit after the transition instead of a bit generated by the recovery circuit. As all bits after transition are recovered, data encoded in an analog signal may be recovered accurately.

Abstract: Digitizing a signal includes sampling and holding an analog signal to yield a sampled signal, where the analog signal includes information. The sampled signal is filtered at a passive filter circuit to yield a filtered signal. The passive filter circuit includes at least one passive element and the filtered signal is characterized by a bandpass response. The filtered signal is quantized to yield a digital signal, where the digital signal corresponds to the analog signal and the digital signal includes the information.