Abstract: A method of providing an automatic repeat request (ARQ) that employs a selective repeat, enabling a transmitting medium access control (MAC) entity at a transmitting station to retransmit those MAC data whose previous transmissions have failed is described. The MAC data is organized into fixed-sized ARQ blocks, with said ARQ blocks being the building blocks of MAC service data units (MSDUs) or MSDU fragments; The transmitting MAC entity assigns a local number and a global number to each ARQ block to be transmitted and identifies ARQ blocks contained in a transmitted MAC protocol data unit (MPDU) by including into the MPDU the local and global numbers of the first ARQ block in that MPDU. A receiving MAC entity at a receiving station determines and acknowledges the reception status of the ARQ blocks received or anticipated.

Abstract: This is a voice activated Hypermedia system using grammatical metadata, the system comprising: a speech user agent; a browsing module; and an information resource. The system may include: embedded intelligence in hypermedia source; a means for processing the actions of a user based on the embedded intelligence; a means for returning a result of the actions to the user. In addition, the hypermedia source maybe a HTML page or an instructional module for communicating allowed actions by a user. The system may also include embedded intelligence as a grammar or reference to a grammar. The grammar may be dynamically added to a speech recognizer. In addition, the actions can come from a speech recognizer. Furthermore, the system may include voice activated hypermedia links and intelligent modules that process information from the information resources for allowing actions from the user. Other devices, systems and methods are also disclosed.

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract: MAP decoder with cascade architecture. Iterative Turbo decoders can use two such cascade MAP decoders with feedback in conjunction with interleaver and deinterleaver where the MAP decoders generate extrinsic information for iterations. The cascade architecture limits the required number of max* blocks which compute the logarithm of a sum of exponentials as part of the BCJR method.

Abstract: The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014 atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.

Abstract: A high precision, curvature compensated bandgap reference circuit with programmable gain is provided. An exemplary bangap reference circuit comprises a curvature compensation circuit configured for compensation of the temperature coefficient characteristic of the bandgap reference circuit, and a programmable gain circuit configured for adjusting the gain the output of the curvature compensation circuit to provide a high precision reference voltage. To facilitate high precision and accuracy, each of the curvature compensation circuit and the programmable gain circuit are configured for trimming during operation/after manufacture. Trimming of the temperature compensation circuit is facilitated by a first digital-to-analog (DAC) device. The programmable gain circuit comprises a gain trimming circuit comprising a second DAC.

Abstract: A digital subscriber line (DSL) modem for a service area interface, which controls the power of its downstream transmissions to minimize far-end crosstalk (FEXT), is disclosed. The disclosed modem has an interface to a low-attenuation upstream facility, such as fiber optic, and includes a digital transceiver and an analog front end that is coupled to a twisted-pair wire facility in a binder. The modem also includes a memory location for storing the feeder distance between a DSL central office and the service area interface, the service area interface also coupled to a subscriber of the CO-fed communications via twisted-pair wire. Power cutback levels are applied to the downstream transmissions from the modem according to the feeder distance, so that the FEXT on the CO-fed signal is minimized without undue data rate degradation.

Abstract: A semiconductor stacked die package adapted to wirelessly transfer data between stacked dies. The package comprises a plurality of dies, each die adjacent another die and each die comprising an infrared transceiver. A first infrared transceiver transfers data to a second infrared transceiver by emitting a pattern of infrared light pulses representative of the data.

Abstract: A PLL lock generator using one circuit (lock detection block) to indicate whether an output clock signal is locked to an input reference signal, and another circuit to determine whether the signals are out-of-lock. A lock generation blocks examines several indications of lock detection before generating a lock signal. Short term fluctuations (such as jitter) in lock and out-of-lock indications may be ignored. An embodiment of lock detection block contains a first flip-flop latching an up signal and clocked by a down signal, and a second flip-flip latching the down signal and clocked by an up signal. The up and down signals may be generated by a phase frequency detector. An examination circuit examines the output of lock detection block to generate the lock indications.

Abstract: A novel and useful apparatus for and method of clock recovery from a serial data stream. The clock recovery mechanism of the present invention provides accurate and fast timing recovery while operative to filter out the effects of noise. The clock recovery mechanism clocks the received serial data into a shift register of N bits, where N is an even number equal to the oversampling factor of the data signal. A timing correction, generated during learning cycles, is applied during the subsequent correction cycle. The timing is adjusted during correction cycles by preloading the reference counter, from which the sampling clock is produced, such that its cycle is either shortened or extended by M clocks, where M corresponds to the required timing correction.

Abstract: In accordance with the teachings of the present invention, a system and method for regulating bridge voltage in a discrete-time hot-wire anemometer is provided. In a particular embodiment, the hot-wire anemometer includes a bridge circuit including a hot-wire resistor, first and second input terminals, and first and second output terminals, the hot-wire resistor having a resistance dependent at least in part on an airflow past the hot-wire resistor. The hot-wire anemometer further includes a first operational amplifier coupled to the output terminals of the bridge circuit, the first operational amplifier operable to generate an output signal in response to a voltage differential across the first and second output terminals of the bridge circuit, and a second operational amplifier operable to generate an output signal in response to the output signal of the first operational amplifier and to a discontinuous time control signal.

Abstract: The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is performed at low speed, and that can fully exploit processibility, by means of input line memory 23 and output line memory 24, which can store image data of one scan line, and are arranged in the input unit and output unit, respectively; the input image data are written in input line memory 23 at the speed of the input image data; the image data that have been written to the input line memory are read at a speed n times faster than the input image data and are sent to processing unit 25 or memory unit 26; processing unit 25 and memory unit 26 receive the image data of one scan line at a speed n times faster than the speed of the input image data, perform a prescribed processing, and then output the processing results at a speed n times faster than the speed of the input image data; the image data output from processing unit 25 or memory unit 26 are selected

Abstract: A method of processing a partial wafer in accordance with one embodiment comprises includes after of loading partial wafer into wafer table of pick and place equipment after saw; downloading wafer map data for the wafer from wafer map data host. If the partial wafer has a reference die then positioning the wafer table to the reference die and then moving the wafer table to the last column of the partial wafer. If the partial wafer does not have a reference die the last column (LCOLUMN) information is obtained from wafer map data header field in one embodiment and using LCOLUMN information remove all dies in the right side of partial wafer map. The wafer table is moved to pseudo reference die which is the first die in the bottom right. The pseudo reference die coordinate (x1, y1) is calculated where x1=first column from right to left that has a die in the wafer map data and y1=first bottom most row in the column x1 from the wafer map data.

Abstract: An actual sense amplifier senses a signal received on a bit line to generate a bit, and a latch latches the bit at a time point specified by a latch enable signal. A tracking circuit generates the latch enable signal in an appropriate time window. The tracking circuit may contain a dummy sense amplifier implemented similar to the actual sense amplifier and a dummy column from which the actual sense amplifier senses a signal received upon accessing the dummy memory array. The latch enable signal may be generated after the dummy sense amplifier generates a bit representing the sensed signal. The time taken by the dummy sense amplifier to generate the bit depends on the load offered by the dummy memory array. Accordingly, the dummy memory array is designed to offer sufficient load to ensure that the latch enable signal is generated in an appropriate time window.

Abstract: Transistor gate structures, encapsulation structures, and fabrication techniques are provided, in which sidewalls of patterned gate structures are conditioned by nitriding the sidewalls of the gate structure, and a silicon nitride encapsulation layer is formed to protect the conditioned sidewalls during manufacturing processing. The conditioning and encapsulation avoid oxidation of gate stack layers, particularly metal gate layers, and also facilitate repairing or restoring stoichiometry of metal and other gate layers that may be damaged or altered during gate patterning.

Abstract: A DSL modem (50). The DSL modem includes a connector (62) comprising a first pair of conductors (IP1, IP2) and a second pair of conductors (OP1, OP2). The DSL modem further includes both circuitry for transmitting according to a DSL protocol (52) and circuitry for receiving according to a DSL protocol (52). Still further, the DSL modem includes switching circuitry (60) operable to selectively switch to a first position to couple the circuitry for transmitting and the circuitry for receiving to the first pair of conductors and to a second position to couple the circuitry for transmitting and the circuitry for receiving to the second pair of conductors. Lastly, the DSL modem includes circuitry (52, CONTROL) for controlling the switching circuitry to switch to one of the first position and the second position and for then detecting whether DSL service exists along the pair of conductors to which the circuitry for transmitting and the circuitry for receiving is then coupled.

Abstract: A bandwidth limited sampling circuit of high linearity may be implemented by using a first circuit portion to limit the bandwidth of the input signals, and using a second circuit portion to sample the bandwidth limited input signal. The first circuit portion and the second circuit portion may be implemented using separate components. In an alternative embodiment, bandwidth limiting is implemented by taking a difference of a sampled input signal from a sampled high frequency components of the input signal.

Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (106) is integrated at the top metal interconnect level (104) and includes surface protection layer (109) for the copper metal (104b) of the top metal interconnect.

Abstract: The present invention provides a system for removing organic contaminants (216) from a copper seed layer that has been deposited on a semiconductor substrate (206). The present invention provides a housing (204) to enclose the semiconductor substrate within. An ultraviolet radiation source (210) is disposed within the housing. A treatment medium (208) is also provided within the housing. The semiconductor substrate is enclosed within the housing and exposed to the treatment medium. The ultraviolet radiation source exposes the semiconductor substrate to ultraviolet radiation, desorbing the contaminants from the seed layer.

Abstract: An information storage and retrieval system (40) and method for operating same has a host device (42) and an information storage device (41), which includes mass data storage means (54), such as a DVD, a DVD RAM, CD-ROM, alone, or in combination. The information storage device (41) includes a cache memory (48) for holding data as it is being written to the mass data storage means (54). The host device (42) is connected to the cache memory (48) to control a size of the cache memory that can be utilized to hold the data to be written to the mass data storage means (54), to control, for instance, the flush, seek, busy, and/or overhead times of the information storage device (41).