Abstract: The present invention provides a method for monitoring a shift in a buried layer in a semiconductor device and a method for manufacturing an integrated circuit using the method for monitoring the shift in the buried layer. The method for monitoring the shift in the buried layer, among other steps, includes forming a buried layer test structure (200) in, on or over a substrate (210) of a semiconductor device, the buried layer test structure (200) including a first test buried layer (230a) located in or on the substrate (210), the first test buried layer (230a) shifted a predetermined distance with respect to a first test feature (240a). The buried layer test structure (200) further includes a second test buried layer (230b) located in the substrate (210), the second test buried layer (23b) shifted a predetermined but different distance with respect to a second test feature (240b).

Abstract: The present invention provides, in one embodiment, An integrated circuit device (100). The integrated circuit device (100) comprises a circuit feature (105) located over a semiconductor substrate (110) and an insulating layer (115) located over the circuit feature (105). A protective overcoat (120) is located over the insulating layer (115) and a metal structure (125) is located over the protective overcoat (120). The metal structure (125) is electrically connected to the circuit feature (105) by an interconnect (130). The metal structure (125) is coated with a conductive encasement (135), the conductive encasement (135) terminating at a perimeter (140) of the metal structure (125). Another embodiment of the invention in a method of manufacturing an integrated circuit device (200).

Abstract: A semiconductor package comprising a die adjacent a lead frame die pad, said lead frame die pad adapted to dissipate heat from the die. The package further comprises a thermally-conductive material abutting the die and a heatsink abutting the thermally-conductive material, said heatsink facing a direction opposite from the lead frame die pad.

Abstract: A method for coupling a heat slug to a lead frame, comprising aligning a heat slug and a lead frame depositing a material between the heat slug and the lead frame, and clamping together the heat slug and the lead frame.

Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.

Abstract: A method of optimally distributing signal power for multiple users over a xDSL or wireless channel considers uses computationally efficient tools to achieve improved crosstalk avoidance. The method chooses between EQPSD and FDS signaling in a fashion that maximizes overall data rate. Rather than choosing EQPSD signaling in regions where there is low self-NEXT, but where the echo is high (relative to signal power), the method selects FDS signaling since the communication system acts in a manner similar to self-NEXT in such regions.

Abstract: A pipeline ADC implemented with both general charge redistribution stages and flip-around charge redistribution stages. Using the flip-around charge redistribution stages leads to reduced power/area consumption, but could lead to accumulation and propagation of errors. general charge redistribution stages are used to control/contain the errors. As a result, the ADC is implemented to achieve an acceptable bit error and power efficiency combination. According to another aspect of the present invention, the first stage is implemented as a flip-around charge redistribution stage (in combination with general charge redistribution stages in subsequent stages) since there is no accumulation of error from prior stages, and implementing the first stage as a flip-around charge redistribution stage gives maximum advantages in power efficiency.

Abstract: Connection circuitry provides for TAP and internal scan test ports to be merged so they both can co-exist and operate from the same set of IC pins and/or core leads or terminals. This arrangement provides for the merged TAP and scan test port interfaces to be selected individually or in groups. Internal Tap Lock circuitry uses only the existing 1149.1 interface signals to produce a Lock Out signal to enable and disable a TMS/CS signal to the TAP circuitry.

Abstract: An improved bond integrity test system is provided by eliminating the spring loaded wire spool cover which contributes to particulate matter, and by addition of a second contact diverter in the wire path. These improvements have been shown to decrease false lifted ball bond reports by 68%, and therefore to improve productivity and accuracy of the test system. Such changes are readily adapted to current bonders, as well as to new designs.

Abstract: In a node failure detection technique at least one supervisory data processing node periodically transmits a receipt acknowledge data packet to each other data processing node. The supervisory data processing node determines a data processing node has failed upon failure to receive a return acknowledge data packet. This acknowledge data packet preferably includes health data concerning its current health operating status. The supervisory data processing node sends a reset data packet to any failed data processing node determined. If the reset does not return the data processing node to normal operation, then routing data at neighboring data processing nodes is altered to route data packets around the failed node.

Abstract: Another embodiment of the instant invention is a method of fabricating a conductive interconnect for providing an electrical connection between a first conductor and a second conductor for an electrical device formed in a semiconductor substrate, the method comprising the steps of: forming a dielectric layer (layer 226 of FIG. 2a) on the first conductor (conductor 222 of FIG. 2a), the dielectric layer having at least one opening which exposes the first conductor; forming a layer of an oxygen-sensitive material (layer 234 of FIG.

Abstract: The charge detection device includes a floating diffusion, a reset transistor, a feed through shielding transistor, and a bias tracking voltage reference generator for biasing an output diode. The reset feed through shielding transistor gate overlaps the reset transistor gate to minimize the reset feed through. The bias tracking voltage reference generator output is adjusted such as to set a predetermined reset time constant for the device and to optimize the detection node performance by minimizing the charge spill back during the reset transistor turning off interval.

Abstract: An aspect of the present invention simplifies the implementation of complex clock designs in field programmable devices (FPD). To implement a circuit logic containing base sequential elements (e.g., D flip-flops) with corresponding circuit clocks, a number of modified sequential elements equaling the number of base sequential elements may be employed. Each modified sequential element (contained in FPD) receives a global clock, corresponding circuit clock and a data value. A base sequential element (contained in modified sequential element) transitions to a next state only after occurrence of a transition on a corresponding circuit clock and the transition to said next state may be timed according to the global clock. By timing the transitions according to the global clock, several undesired results may be avoided.

Abstract: A system and method of calibrating a digital-to-analog converter (DAC) such as a resistor string DAC that reduces costs by making more efficient use of integrated circuit chip area, without requiring analog calibration circuits. The DAC calibration system includes a main DAC to be calibrated, a memory, and calibration logic circuitry for performing arithmetical operations. The memory stores a predetermined number of digital code values in respective memory locations, which are indexed by corresponding voltage values. The digital code values represent DAC input code values which, when applied to the main DAC, would generate the corresponding index voltage values as DAC output voltage levels. The stored DAC input code values and the corresponding DAC output voltage levels, which are determined using an external tester, define piecewise linear (PWL) breakpoint code values of a PWL approximation of the DAC transfer function.

Abstract: A method of producing a correction signal includes receiving a predetermined data sequence (500). The data sequence is sampled at predetermined times, thereby producing a sampled data sequence (522, 532). The sampled data sequence is separated into first and second sampled data sequences. A ratio is calculated (550, 558) from the first and second sampled data sequences. A correction signal is produced (556, 564) in response to the ratio.

Abstract: A class-D amplifier circuit (30; 30?) providing improved open-loop error for base-band frequencies, such as the audio band, is disclosed. The amplifier circuit (30; 30?) includes a comparator (35) for generating a pulse-width-modulated output signal that is applied to an output power stage (37). An LC filter (32) is at the output of the power stage (37). The amplifier circuit (30; 30?) includes a loop filter having multiple feedback loop paths, with at least one feedback loop path coupled to the output of the power stage (37), and optionally, at least one feedback loop path coupled to the output of the LC filter (32). The transfer function (Hmae(s)) of the loop filter has a real part that has a much steeper slope (on the order of 80 dB/decade) at frequencies above the pulse-width-modulation switching frequency than the slope of its magnitude characteristic at frequencies below this switching frequency.

Abstract: A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform. The samples can be manipulated to provide gain adjustment to the second voltage waveform. The samples are obtained by charging a sampling capacitance in response to a current waveform that corresponds to the first voltage waveform. The use of different sampling capacitances during respective predetermined time intervals permits the signal strength of the first waveform to be determined from observation of the second waveform.

Abstract: A combined pressure and temperature transducer (10) particularly adapted for high temperature fluids has a sensing element assembly mounted at the tip of a tubular probe (20) which is arranged for placement in a fluid flow path. A sensing element (12) includes a pressure responsive diaphragm (12g) closing the open end of the tubular probe and being provided with piezo-resistive gauge elements bonded to the diaphragm. Wires are bonded between the gauge elements and a first, heat resistant, printed circuit board (PCB). The first PCB, together with the piezo-resistive elements, form a Wheatstone bridge. An inner connector (26) mounts elongated, axial stress absorbing contacts connecting the first PCB at one end of the inner connector with a second printed circuit board (PCB) mounted at the opposite end of the inner connector physically removed from the sensing element and first PCB and away from the fluid flow path. The second PCB mounts signal conditioning and amplifying electronics.

Abstract: The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.

Abstract: A package is disclosed, which includes a substrate, a solder masker, and a first aperture through the solder mask. The substrate has a surface on which metal traces are formed. The solder mask covers at least a portion of the surface of the substrate. And the first aperture through the solder mask exposes a plurality of the metal traces.