Abstract: A routable lead frame (RLF) substrate has a conductive layer having first- and second-side traces having first fingers and second fingers, respectively, which are interdigitated with each other. A via layer is over the conductive layer. A first-side conductive via of the via layer is conductively coupled to the first-side trace. A second-side conductive via of the via layer is conductively coupled to the second-side trace. Dielectric molding material is disposed between the interdigitated fingers of the conductive layer and between the first-side conductive via and the second-side conductive via. The fingers and vias form an interdigital capacitor (IDC) useful in impedance matching and filtering.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to evict in a dual datapath victim cache system. An example apparatus includes a cache storage, a cache controller operable to receive a first memory operation and a second memory operation concurrently, comparison logic operable to identify if the first and second memory operations missed in the cache storage, and a replacement policy component operable to, when at least one of the first and second memory operations corresponds to a miss in the cache storage, reserve an entry in the cache storage to evict based on the first and second memory operations.

Abstract: An example apparatus includes: pass gate circuitry having a first terminal and a second terminal; process tracker circuitry having a first terminal and a second terminal, the first terminal of the process tracker circuitry coupled to the first terminal of the pass gate circuitry; and temperature compensation circuitry having a first terminal and a second terminal, the first terminal of the temperature compensation circuitry coupled to the second terminal of the process tracker circuitry, and the second terminal of the temperature compensation circuitry coupled to the second terminal of the pass gate circuitry.

Abstract: A method for decoding encoded blocks of pixels from an encoded video bit stream is provided that includes decoding a block vector corresponding to an encoded block of pixels from the encoded bit stream, verifying that the block vector indicates a block of reconstructed pixels in a search area including reconstructed pixels of a largest coding unit (LCU) including the encoded block of pixels and N left neighboring reconstructed LCUs of the LCU, and decoding the encoded block of pixels, wherein the block of reconstructed pixels is used as a predictor for the encoded block of pixels.

Abstract: An integrated circuit (IC) assembly includes a first power stage adapted to receive an input voltage and a second power stage adapted to provide an isolated output voltage. The IC also includes a transformer coupled between the first and second power stages. The IC further includes a detuning circuit coupled to the transformer, and a receiver circuit coupled to the first power stage. The receiver circuit includes an integrator configured to integrate a switching signal within the first power stage.

Abstract: In examples, a semiconductor package comprises a conductive terminal; a semiconductor die including a device side having circuitry formed therein, the device side facing toward the conductive terminal; and a substrate coupled to the conductive terminal and to the device side of the semiconductor die. The substrate includes a first metal layer coupled to first and second vias extending toward and coupled to either the device side of the semiconductor die or the conductive terminal. The substrate includes a second metal layer electrically isolated from the first metal layer by an insulation layer between the first and second metal layers, the second metal layer coupled to a third via extending toward and coupled to either the conductive terminal or the semiconductor die. The first and second metal layers form a Marchand balun.

Abstract: A lead frame includes a metal structure having opposite first and second sides and prospective device portions having leads with first and second lateral sides extending from a tie bar toward a die attach pad. One or more of the leads includes a first indent in the first lateral side that extends to the first side of the metal structure, and a second indent that extends to the second side of the metal to reduce saw blade loading and mitigate saw burr and lead smear during package singulation. A packaged electronic device includes a package structure, a semiconductor die enclosed by the package structure, and leads having a first side, a second side, and first and second lateral sides, where the leads include a first indent in the first lateral side that extends to the first side, and a second indent that extends to the second side of the lead.

Abstract: An example apparatus includes: current driver circuitry configured to supply power to a stepper motor; and controller circuitry coupled to the current driver circuitry, the controller circuitry configured to: determine a first duty cycle of power transferred to the stepper motor by the current driver circuitry during a first operation of the stepper motor, the first operation to supply power using currents of a target magnitude; determine an previous duty cycle of power transferred to the stepper motor by the current driver circuitry during a second operation of the stepper motor, the second operation of the stepper motor to supply power using currents of the target magnitude; and determine changes in a mechanical load applied to the stepper motor responsive to a comparison of the first duty cycle to the previous duty cycle.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to forward and invalidate inflight data in a store queue. An example apparatus includes a cache storage, a cache controller coupled to the cache storage and operable to receive a first memory operation, determine that the first memory operation corresponds to a read miss in the cache storage, determine a victim address in the cache storage to evict in response to the read miss, issue a read-invalidate command that specifies the victim address, compare the victim address to a set of addresses associated with a set of memory operations being processed by the cache controller, and in response to the victim address matching a first address of the set of addresses corresponding to a second memory operation of the set of memory operations, provide data associated with the second memory operation.

Abstract: A method for automatic exposure (AE) control is provided that includes receiving statistics for AE control for an image from an image signal processor (ISP) coupled to an image sensor generating the image, computing an exposure value at a current time t (EV(t)) using a cost function based on target characteristics of an image, wherein computation of the cost function uses the statistics, and computing AE settings for the image sensor based on EV(t).

Abstract: An apparatus an apparatus includes a light source and freeform optics optically coupled to the light source. The apparatus also includes a spatial light modulator (SLM) optically coupled to the freeform optics and a prism optically coupled between the freeform optics and the SLM. Additionally, the apparatus includes eyepiece optics optically coupled to the prism.

Abstract: Described examples include an apparatus including a package substrate having a die attach pad and a first semiconductor die on the die attach pad, the first semiconductor die including a transmitter. The apparatus also includes an assembly having a first plate coupled to the transmitter, a second plate separated from the first plate by a dielectric and a second semiconductor die on the die attach pad, the second semiconductor die including a receiver coupled to the second plate.

Abstract: A radar device includes processing circuitry to perform operations to identify corrupted data samples in an initial time-domain data set generated from return signals reflected from a target object and also signals from an interfering object causing the corruption. The processing circuitry also performs operations starting on the initial time-domain data set to generate reconstructed data corresponding to the corrupted data samples. An uncorrupted time-domain data set is then generated based on the initial time-domain data set and the corrupted data samples, and repaired time-domain data set is generated based on the uncorrupted time-domain data set and the reconstructed data. The operations performed include thresholding, transforming, inverse transforming, subtracting, and/or combining. The processing circuitry may be hard coded and/or be configured to execute software instructions stored in a memory to perform the processing.

Abstract: A circuit includes a capture subsystem and digital pre-distortion (DPD) circuitry. The capture subsystem is configured to capture a set of signal samples responsive to a capture enable signal. The DPD circuitry is configured to generate a signal statistics signal based on an input signal, generate a set of DPD coefficients based on the set of signal samples, and apply DPD correction to the input signal to produce an output signal based on the signal statistics signal and the set of DPD coefficients. The set of signal samples includes samples of the signal statistics signal.

Abstract: A circuit includes a first transistor coupled between a discharge terminal and a ground terminal. The first transistor has a first control terminal. A resistor is coupled between a power terminal and the first control terminal. A second transistor has a second control terminal coupled to the discharge terminal. A rectifying device is coupled between the resistor and the second transistor.

Abstract: A semiconductor device includes: a package substrate having a device mount surface and on an opposite bottom side surface; at least one semiconductor die mounted on the device mount surface; and leads having a base portion attached to the device mount surface and having an internal portion extending away from a first bend at a first angle, the internal portion of the leads extending to a second bend, a remaining portion of the leads extending from the second bend and lying in a horizontal plane parallel to the device mount surface, the leads having a third bend in the remaining portion forming terminals extending at a second angle with respect to the horizontal plane of the remaining portion. Mold compound covers the device mount surface, portions of the leads, and the semiconductor die. The terminals are exposed at a board side surface of the mold compound.

Abstract: An electronic device includes a package structure, a conductive terminal exposed outside the package structure, a semiconductor die in the package structure, and a bond wire having contiguous first and second portions. The first portion has a first end and a second end, the first end connected to the semiconductor die by a first bond and the second end connected to the conductive terminal by a second bond. The second portion has a first end and a second end, the first end of the second portion connected to the second end of the first portion, and the second end of the second portion connected to the conductive terminal by a third bond.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed corresponding to current limit circuitry with controlled current variation. An example circuit includes a voltage regulator configured to control a first transistor to regulate a supply voltage to a regulated voltage; and current limit circuitry configured to enable a second transistor to lower an output current when a voltage at a control terminal of the first transistor satisfies a threshold.

Abstract: A method and apparatus for a low complexity transform unit partitioning structure for High Efficiency Video Coding (HEVC). The method includes determining prediction unit size of a coding unit, and setting the size of transform unit size of Y, U and V according to the prediction unit size of the coding unit.

Abstract: A switching converter controller includes: mode control logic; and a pulse-frequency modulation (PFM) timer circuit coupled to the mode control logic. The PFM timer circuit includes: a first terminal; a second terminal; a digital-to-analog converter (DAC); a current source; a capacitor; and a comparator. A first terminal of the DAC is coupled to the first terminal of the PFM timer circuit. The current source has a first terminal, a second terminal, and a third terminal. The second terminal of the current source is coupled to a second terminal of the DAC. A first terminal of the capacitor is coupled to the first terminal of the current source. The comparator has first, second, and third terminals. The first terminal of the comparator is coupled to the first terminal of the capacitor. The third terminal of the comparator is coupled to the second terminal of the PFM timer circuit.