Abstract: An apparatus includes a charge transfer circuit, a control circuit, and a processing circuit. The charge transfer circuit has a first terminal, a second terminal, a third terminal, and a control input. The control circuit has a control output coupled to the control input. The processing circuit has a first input, a second input, and an output. The processing circuit is configured to receive a first signal at the first input and receive a second signal at the second input. The first signal represents a current through the charge transfer circuit. The second signal represents at least one of a first voltage between the first and second terminals or a second voltage between the second and third terminals. The processing circuit is also configured to provide a third signal based on the first and second signals at the output.

Abstract: A circuit includes a bias current generator, a temperature compensation circuit, and a Hall effect sensor. The bias current generator has a first input, a second input, a first terminal, and a second terminal. The bias current generator includes a resistor circuit having a first terminal and a second terminal coupled to the first terminal and the second terminal of the bias current generator respectively. The temperature compensation circuit has a first input, a second input coupled to the first input of the bias current generator, and an output coupled to the second input of the bias current generator. The Hall effect sensor has a first terminal coupled to the first terminal of the bias current generator, a second terminal, a third terminal, and a fourth terminal.

Abstract: An example apparatus includes: a bus connection including a common terminal; a first data terminal; and a second data terminal; an amplifier having an input terminal and an output terminal, the input terminal of the amplifier coupled to the common terminal; charge pump circuitry having an input terminal, a first output terminal, and a second output terminal, the input terminal of the charge pump circuitry coupled to the output terminal of the amplifier; receiver circuitry having an input terminal, a first supply terminal, and a second supply terminal, the input terminal of the receiver circuitry coupled to the first data terminal; and transmitter circuitry having an output terminal, a first supply terminal, and a second supply terminal, the output terminal of the transmitter circuitry coupled to the second data terminal, the first supply terminal of the transmitter circuitry coupled to the first output terminal of the charge pump circuitry.

Abstract: A method for sparse optical flow based tracking in a computer vision system is provided that includes detecting feature points in a frame captured by a monocular camera in the computer vision system to generate a plurality of detected feature points, generating a binary image indicating locations of the detected feature points with a bit value of one, wherein all other locations in the binary image have a bit value of zero, generating another binary image indicating neighborhoods of currently tracked points, wherein locations of the neighborhoods in the binary image have a bit value of zero and all other locations in the binary image have a bit value of one, and performing a binary AND of the two binary images to generate another binary image, wherein locations in the binary image having a bit value of one indicate new feature points detected in the frame.

Abstract: In described examples, an integrated circuit (IC) includes a matrix multiplication accelerator including a first memory, a second memory, and a memory controller. The second memory is configured to store multiple rows of an input feature map on a single line of cells of the memory, and to store a filter kernel. The memory controller reads multiple contiguous memory vectors of the second memory, different ones of the contiguous memory vectors corresponding to different portions of the input feature map. The memory controller also replaces (with padding zeroes) values of respective ones of the contiguous memory vectors. The number and location of replaced values are selected in response to a column index of an element of the filter kernel in response to which the respective contiguous memory vector is read. Zero padded contiguous memory vectors are written to the first memory.

Abstract: Within a wireless network, feedback information from user equipment (UE) to a control node (eNodeB) is necessary to support various functions. A UE receives an allocation from the eNodeB comprising a plurality of periodic transmission instances for a channel quality indicator (CQI) and a schedule comprising a plurality of periodic transmission instances for a rank indicator (RI), wherein the CQI comprises RI and other CQI fields. The UE then transmits an RI without transmitting the other CQI fields in a transmission instance allocated for both RI and other CQI fields.

Abstract: A method of fabricating an electronic device includes depositing a metal layer having external leads on a carrier. A photoresist material layer is patterned on the leads. A dielectric layer is formed over the metal layer such that surfaces of metal pillars from the metal layer are exposed. The photoresist material layer is removed from the leads, and the dielectric layer and the metal layer are removed from the carrier. A die is attached to the first surface of the dielectric layer. The die includes contacts on a surface of the die that contacts the dielectric layer such that the contacts are aligned with and connect to the exposed surfaces of the metal pillars. A mold compound is formed over the die, the dielectric layer, the metal traces, and the metal pillars of the metal layer, but not over the leads of the metal layer.

Abstract: An electronic device includes a metal heat slug, a semiconductor die, and a package structure. The metal heat slug has a first portion, a second portion, and a third portion, the second portion is spaced apart from the first portion, and the third portion connects the first and second portions. The semiconductor die is attached to the third portion of the metal heat slug to measure a current of the third portion of the metal heat slug, and the package structure encloses the semiconductor die and the third portion of the metal heat slug and exposes sides of the first and second portions of the metal heat slug.

Abstract: A method of forming an integrated circuit by forming a first silicon surface, forming a second silicon surface, forming a first silicide blocking layer along the first silicon surface and along the second silicon surface, and forming a second silicide blocking layer along the first silicide blocking layer. The forming of each of the first silicide blocking layer and the second silicide blocking layer includes forming a plasma enhanced chemical vapor deposition (PECVD) layer and exposing the PECVD layer to a noble gas for a time duration. Thereafter, the method removes a portion of the second silicide blocking layer and an underlying portion of the first silicide blocking layer to expose the first silicon surface while leaving at least the first silicide blocking layer over the second silicon surface and silicides the first silicon surface.

Abstract: An example apparatus includes: rectifier circuitry including: a first resistor having a terminal; a second resistor having a terminal; a first transistor having a first terminal, a second terminal, and a control terminal; and a second transistor having a first terminal, a second terminal, and a control terminal; reference circuitry having a first input, a second input, a third input, a fourth input, and an output, the first input of the reference circuitry coupled to the control terminal of the first transistor, the second input of the reference circuitry coupled to the terminal of the second resistor and first terminal of the second transistor, the third input of the reference circuitry coupled to the control terminal of the second transistor, the fourth input of the reference circuitry coupled to the terminal of the first resistor and the first terminal of the first transistor.

Abstract: An electronic system includes a bipolar junction transistor (BJT) input stage circuit having a first BJT input, a second BJT input, a first BJT output, a second BJT output, and a BJT voltage input. An amplifier has a first amplifier input, a second amplifier input, and an amplifier output. The first amplifier input is coupled to the first BJT output and the second amplifier input is coupled to the second BJT output. The second BJT input is coupled to the amplifier output. A base current compensator has a first base compensator output, a second base compensator output, and a base compensator voltage output. The first base compensator output is coupled to the first BJT input and the second base compensator output is coupled to the second BJT input. The base compensator voltage output is coupled to the BJT voltage input.

Abstract: An electronic package includes an electronic component including terminals, a plurality of leads, at least some of the leads being electrically coupled to the terminals within the electronic package, and a mold compound covering the electronic component and partially covering the leads. Each of the leads include an exposed bottom face coplanar with a bottom surface of the mold compound and an exposed end face coplanar with one of a plurality of side surfaces of the mold compound. For at least some of the leads, the exposed end face includes a narrow portion forming a concave recess, the narrow portion being between top and bottom edges of the exposed end face.

Abstract: A test load board includes a PCB (printed circuit board) with pads for a probe of a tester. The test load board also includes a contactor that includes contact points for connecting leads of a DUT (device under test). The test load board further includes an RFID (radio frequency identification) tag affixed to the PCB. The RFID tag is loaded with a unique identifier (ID) of the test load board.

Abstract: Disclosed embodiments include a decision feedback equalizer (DFE) comprising an N-bit parallel input adapted to be coupled to a communication channel and configured to receive consecutive communication symbols, a first DFE path including a first path input configured to receive communication symbols, and a first adder having a first adder input coupled to the first path input. There is a first DFE filter having outputs responsive to the first DFE filter inputs, the outputs coupled to the second adder input. The DFE includes a first path having a first slicer and a first multiplexer, a first path multiplexer output, and a second DFE path including a second path input configured to receive a second communication symbol, a second adder, a second DFE filter, a second slicer, and a second multiplexer.

Abstract: In an example, a system includes a first transistor having a control terminal, a first terminal, and a second terminal. The system also includes a resistor having first and second terminals, the first terminal of the resistor coupled to the control terminal of the first transistor, and the second terminal of the resistor coupled to a first voltage terminal. The system includes a second transistor having a control terminal, a first terminal, and a second terminal, where the first terminal of the second transistor is coupled to the control terminal of the first transistor and to the first terminal of the resistor, and the second terminal of the second transistor is coupled to the control terminal of the second transistor.

Abstract: A method is provided. In some examples, the method includes initiating, by a host application in a station, resumption of target wakeup time (TWT) service between the station and an access point. In addition, the method includes transmitting, by a communication interface in the station to the access point, a request to resume the TWT service. The method further includes generating, by the host application, data for transmission to the access point and transmitting, by the communication interface to the access point, the generated data. The method also includes receiving, by the station after transmitting the generated data, a response from the access point and initiating, by the host application, suspension of the TWT service. Moreover, the method includes transmitting, by the communication interface to the access point, a request to suspend the TWT service.

Abstract: In examples, a microelectromechanical device comprises a moveable element configured to contact a portion of a surface, and an ionic liquid on the portion of the surface.

Abstract: In described examples, a first device on a first surface of a substrate is coupled to a structure arranged on a second surface of the substrate. In at least one example, a first conductor arranged on the first surface is coupled to circuitry of the first device. An elevated portion of the first conductor is supported by disposing an encapsulate and curing the encapsulate. The first conductor is severed by cutting the encapsulate and the first conductor. A second conductor is coupled to the first conductor. The second conductor is coupled to the structure arranged on the second surface of the substrate.

Abstract: An example apparatus includes: current source circuitry having a first terminal and a second terminal; current sink circuitry having a first terminal and a second terminal; a first transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the first transistor coupled to the first terminal of the current source circuitry; a second transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the second transistor coupled to the first terminal of the current sink circuitry; and a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the second terminal of the first transistor and the second terminal of the second transistor, the second terminal of the capacitor coupled to the second terminal of the current source circuitry, and the second terminal of the current sink circuitry.

Abstract: Methods and apparatus are disclosed to protect secure assets using scan operations. One example apparatus includes logic circuitry including a scan chain that includes data storage elements and design logic coupled to the scan chain. The example apparatus also includes data storage to store secure data. The design logic is coupled to the data storage. The example apparatus also includes a security controller to transition the apparatus out of a secure mode of operation. The transition includes the security controller to cause the scan chain to serially shift secure scan data from an input of the scan chain into each data storage element of the data storage elements of the scan chain.