Abstract: An example device includes a screen, a first light source configured to emit a first light at a first angle during a first time period and a second light source configured to emit a second light at a second angle during a second time period. The second angle is different than the first angle. The second time period is different than the first time period. The device includes a spatial light modulator configured to provide a first view of digital content based on the first angle of the first light emitted during the first time period and a second view of the digital content based on the second angle of the second light emitted during the second time period and projection optics configured to project the first view and the second view for presentation via the screen.

Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.

Abstract: A family of digital logic functions has the same specifications for input and output voltages and the same number of bond pads. A digital logic integrated circuit for the family includes a substrate of semiconductor material having a core area and a peripheral area; a certain number of bond pads formed in the peripheral area, the certain number of bond pads determining the total area of the substrate; programmable digital logic transistor circuitry formed in the core area for each of the digital logic functions in the family; programmable input and output circuitry formed in the peripheral area; programming circuitry for programming the programmable digital logic transistor circuitry into a selected digital logic function; and programmable input and output means for programming the input and output circuitry into input and output circuits for the selected digital logic function.

Abstract: A system includes a plurality of antennas, an access control mechanism, and a computing resource. The computing resource is configured to initiate each of multiple antennas to transmit a wireless signal and receive values indicative of signal strength of the wireless signals from the multiple antennas. The computing resource also is configured to calculate a position of a wireless electrical device based on the received values and calculate an error value of the calculated position of the wireless electrical device. Further, the computing resource is configured to determine that the error value is greater than an error threshold and to disable the access control mechanism.

Abstract: Described embodiments include a gate drive circuit with a first transistor coupled between an input voltage terminal and a switching terminal, and having a first control terminal. A second transistor is coupled between the switching terminal and ground, and has a second control terminal. A first driver circuit has a first driver output coupled to the first control terminal, a first positive supply input coupled to a bootstrap voltage terminal, and a first negative supply input coupled to the switching terminal. A second driver circuit has a second driver output coupled to the second control terminal, a second positive supply input coupled to a driver supply, and a first negative supply input coupled to ground. An active clamp circuit is coupled between the driver supply and ground, and prevents a voltage between the driver supply and ground from exceeding a threshold voltage.

Abstract: A circuit includes a semiconductor substrate and an integrated passive device. The integrated passive device is on a surface of the semiconductor substrate. The integrated passive device is in a metal layer on the semiconductor substrate. The metal layer is at least tens of micrometers thick. The integrated passive device may be an inductor or a capacitor in some examples.

Abstract: An example apparatus includes: a supply terminal; a first inductor having a first terminal and a second terminal; a second inductor having a first terminal and a second terminal, the first terminal of the second inductor coupled to the supply terminal and the first terminal of the first inductor; a first resistor having a first terminal and a second terminal, the first terminal of the first resistor coupled to the second terminal of the first inductor; a second resistor having a first terminal and a second terminal, the first terminal of the second resistor coupled to the second terminal of the second inductor; a first transmission line having a first terminal and a second terminal, the first terminal of the first transmission line coupled to the second terminal of the first resistor; a second transmission line having a first terminal and a second terminal.

Abstract: The techniques and circuits, described herein, include solutions for auto-zeroing in auto-zero amplifiers in the presence of high frequency alternating current (AC) noise. In some aspects, first and second inputs of an auto-zero amplifier are coupled to a differential voltage with high AC noise. During an auto-zero phase, a first switching network decouples the inputs of a first amplifier, comprised within the auto-zero amplifier, from the differential voltage with high AC noise. In some examples, the inputs of the first amplifier may be connected to a regulated direct current (DC) voltage. The regulated DC voltage provides a more accurate auto-zero for the auto-zero amplifier, such that higher overall accuracy is achieved during an operation phase.

Abstract: An apparatus includes a switch assembly having first and second switch terminals and a control terminal. The switch assembly includes a leakage attenuation circuit. The switch assembly is configured to, responsive to the control terminal having a first state, connect the first switch terminal to the second switch terminal and disconnect a circuit terminal of the leakage attenuation circuit from the first switch terminal. The switch assembly is configured to, responsive to the control terminal having a second state, connect the terminal of the leakage attenuation circuit to the first switch terminal and disconnect the first switch terminal from the second switch terminal.

Abstract: A circuit includes: integrated circuit (IC) layers; a cavity formed in at least one of the IC layers; and a micro-acoustic resonator suspended in the cavity by an anchor. The anchor includes: a bridge portion coupled to the micro-acoustic resonator and extending over the cavity; a first acoustic reflector portion adjacent the bridge portion, extending over the cavity, and oriented differently than the bridge portion; and a second acoustic reflector portion adjacent the first acoustic reflector portion, extending over the cavity, and oriented differently than the first acoustic reflector portion.

Abstract: A circuit device includes an interface circuit configured to generate a first network packet and a second network packet. The interface circuit includes preemption circuitry and transmission circuitry. The preemption circuitry is configured to cause the first network packet to be generated as a set of packet fragments that includes a first packet fragment and a second packet fragment and cause the second network packet to be transmitted between the first packet fragment and the second packet fragment. The transmission circuitry is configured to transmit the first packet fragment of the first network packet, the second network packet, and the second packet fragment of the second network packet.

Abstract: A motor controller adapted to be coupled to a motor having a rotor. The motor controller includes a storage device containing software. The motor controller also includes a processor core coupled to the storage device and adapted to be coupled to the motor. The processor core is configured to operate the motor in an open-loop control in response to determining a speed of the rotor determined based on an inverse exponential function with respect to time.

Abstract: In described examples, a switched capacitor circuit includes an amplifier that generates a first output signal in response to a first sampled input signal. A second sampling circuit is coupled to the amplifier and generates an output signal in response to the first output signal. A first current boost circuit is coupled to the amplifier and the second sampling circuit and provides current to the second sampling circuit when the first output signal is below a first threshold. A second current boost circuit is coupled to the amplifier and the second sampling circuit and receives current from the second sampling circuit when the first output signal is above a second threshold.

Abstract: An inductor-inductor-capacitor (LLC) converter may include a control system that holds a duty cycle of control signals at a desired ratio, such as 50%. The control system may include a counter that is configured to count up and down and is further configured to generate event signals that are received at the inputs of a latch. An event signal may cause and output value of the latch to change from high to low or vice versa. There may be further circuits to add delay and/or inversion to generate multiple control signals from the output of the latch. Furthermore, the counter may be configured to switch from counting up to counting down in response to a comparator output.

Abstract: An integrated circuit (IC) package includes a mold compound. A first interconnect of the IC package is encased in the mold compound. The first interconnect includes a first set of leads protruding from a first side of the mold compound along a first row and a second set of leads protruding from a second side of the mold compound along a second row, wherein the first row and the second row are in a first plane. A second interconnect of the IC package is also encased in the mold compound. The second interconnect includes a third set of leads protruding from the first side of the mold compound along a third row and a fourth set of leads protruding from the second side of the mold compound along a fourth row. The third row and the fourth row are in a second plane.

Abstract: An apparatus includes micromirrors in rows and columns of a two-dimensional (2D) array, electrode lines coupled to the micromirrors, where the electrode lines are coupled to respective sets of the micromirrors, and signal driving circuits coupled to the electrode lines, the signal driving circuits configured to control the respective sets of the micromirrors via respective electrode lines.

Abstract: A method is provided that includes displaying packages for a semiconductor product in a graphical user interface (GUI), by at least one processor, wherein each package includes design resources for a respective design use case for the semiconductor product, and displaying, by the at least one processor, design resources included in a package of the packages in the GUI responsive to user selection of the package.

Abstract: A Wi-Fi device in a WLAN network includes a processor and a transceiver adapted to be coupled to an antenna, and a power saving medium access in congested network environments algorithm that is activated after a Wi-Fi connection is established with its access point (AP). A Traffic Indication Map (TIM) bitmap in a TIM information element received in a beacon frame from the AP is analyzed to determine whether more than a predetermined number of bits (X) are set to indicate the AP has ?1 buffered frame for ones of the Wi-Fi devices to conclude whether the WLAN is in a congested environment. When in a congested environment, transmissions responsive to the beacon are postponed by entering a sleep mode for a random period of time (P). After P expires, the sleep mode is exited and a poll frame is transmitted to the AP to try to gain medium access.

Abstract: Embodiments disclosed herein relate to synchronizing signals across multiple independent clock domains. In an example, a synchronizer flip-flop circuit is provided. The synchronizer flip-flop circuit includes a first latch sub-circuit coupled to receive an input and a second latch sub-circuit coupled to the first latch sub-circuit. The first latch sub-circuit includes a first group of inverters, a first diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a first bias voltage to each inverter of the first group of inverters, and a second diode-connected transistor coupled in parallel to each inverter of the first group of inverters and configured to provide a second bias voltage to each inverter of the first group of inverters.

Abstract: An integrated circuit includes a semiconductor die, a package substrate having opposite first and second surfaces, where the first surface includes a first metal pad, the second surface includes a second metal pad and a third metal pad. The semiconductor die is mounted on the second metal pad and the third metal pad by respective first and second metal interconnects. The package substrate includes a circuit with a single-ended terminal and a pair of differential terminals, where the single-ended terminal coupled to the first metal pad. The backage substrate also includes a metal layer including a first meandered conductor and a second meandered conductor. The first meandered conductor is coupled between a first terminal of the pair of differential terminals and the second metal pad. The second meandered conductor is coupled between a second terminal of the pair of differential terminals and the third metal pad.