Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream. Once fetched data elements in the data stream are disposed in lanes in a stream head register in the fixed order. Some lanes may be invalid, for example when the number of remaining data elements are less than the number of lanes in the stream head register. The streaming engine automatically produces a valid data word stored in a stream valid register indicating lanes holding valid data. The data in the stream valid register may be automatically stored in a predicate register or otherwise made available. This data can be used to control vector SIMD operations or may be combined with other predicate register data.

Abstract: An acoustic-wave device includes a first electrode located over a substrate. A piezoelectric film is located over the first electrode and at least partially overlaps the first electrode. A second electrode is located over the piezoelectric film and at least partially overlaps the first electrode and the piezoelectric film. A temperature sensor is located in a same layer level as the first or second electrode. A heater may also be located in a same layer level as the first electrode. A closed-loop system may operate using the temperature sensor and the heater to maintain an operating temperature that provides highly stable operation.

Abstract: An integrated circuit includes a semiconductor substrate with a semiconductor surface layer having a first conductivity type and a top surface, a diode including a buried region within the surface layer, the buried region having an opposite second conductivity type and being spaced apart from the top surface by a portion of the semiconductor surface layer having the first conductivity type, a dielectric layer over the surface layer, and a metal layer located over the dielectric layer and including an aperture extending laterally in a first direction over the semiconductor surface layer and laterally spaced apart from the buried region in a second direction.

Abstract: A circuit includes a semiconductor substrate, a first ground terminal, a second ground terminal, a driver circuit, a capacitor, a receiver circuit, and a substrate bias circuit. The driver circuit is on the semiconductor substrate. The driver circuit is coupled to the first ground terminal, and has a first output and a second output. The capacitor has a first terminal coupled to the first output of the driver circuit and a second terminal. The receiver circuit is on the semiconductor substrate. The receiver circuit is coupled to the second ground terminal, and has a first input coupled to the second terminal of the capacitor, and a second input coupled to the second output of the driver circuit. The substrate bias circuit has a first input coupled to the first ground terminal, a second input coupled to the second ground terminal, and an output coupled to the semiconductor substrate.

Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

Abstract: An example apparatus includes: calibration circuitry configured to determine a second current at a second terminal of a second impedance circuit based on a first parasitic capacitance, a first impedance value, a third impedance value, a first voltage, and a second voltage; determine a third voltage at a second terminal of a second impedance circuit based on the first parasitic capacitance, a second impedance value, the third impedance value, the second voltage, and the second current; and determine a second parasitic capacitance between the second terminal of the second impedance circuit and the second terminal of a fifth impedance circuit based on the second current, the third voltage, a third current at the second terminal of the fifth impedance circuit, and a fourth voltage at the second terminal of the fifth impedance circuit.

Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

Abstract: A method is described herein. The method generally includes receiving stream parameters that defines an array, wherein the stream parameters include a first null element count and a second null element count. The method generally includes forming a stream of vectors for the multidimensional array responsive to the stream parameters. The stream of vectors generally includes a vector of null elements at a beginning of the stream of vectors based on the first null element count. The stream of vectors generally includes a null element at a beginning of each vector of the stream of vectors based on the second null element count. The stream of vectors generally includes a set of data distributed across a subset of the stream of vectors. The method generally includes providing the stream of vectors.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.

Abstract: A method for digital predistortion (DPD) calibration in a wireless communication device is provided that includes transmitting, by transmission circuitry of the wireless communication device, a plurality of pulses, where each pulse corresponds to an amplitude step in a pattern of amplitude steps, where the amplitude steps are separated by silence gaps, receiving each pulse in receiver circuitry of the wireless communication device, generating, by an accumulator component of the wireless communication device, an accumulated sample for each pulse based on a plurality of samples output by the receiver circuitry for the pulse, and computing, by a processor of the wireless communication device, amplitude dependent gain (AM/AM) and amplitude dependent phase shift (AM/PM) values for each accumulated sample.

Abstract: In an embodiment, a method includes receiving a logical address from a primary device and determining an address header based on the logical address. The method also includes determining an offset value based on the address header and applying the offset value to a first portion of the logical address to create an offset address portion. The method further includes generating a physical address that includes the address header and the offset address portion and accessing a physical resource using the physical address.

Abstract: Aspects of the description provide for a circuit. In some examples, the circuit includes a input pair of transistors, a bias transistor having a bias transistor gate, a bias transistor drain, and a bias transistor source, the bias transistor drain coupled to the input pair of transistors and the bias transistor source coupled to ground, and a resistor coupled between the bias transistor gate and the input pair of transistors.

Abstract: In examples, an apparatus comprises a package substrate, a first semiconductor die, and a second semiconductor die. The package substrate has opposing first and second surfaces and including a first coil and a second coil in a first metal layer of the package substrate and a third coil and a fourth coil in a second metal layer of the package substrate. The first coil has a set of first terminals, the second coil has a set of second terminals, the third coil has a set of third terminals, and the fourth coils has a set of fourth terminals. The first semiconductor die is coupled to the first surface and to the sets of the first and second terminals. The second semiconductor die is coupled to the second surface and to the sets of the third and fourth terminals.

Abstract: A streaming engine employed in a digital signal processor specified a fixed data stream. Once started the data stream is read only and cannot be written. Once fetched, the data stream is stored in a first-in-first-out buffer for presentation to functional units in the fixed order. Data use by the functional unit is controlled using the input operand fields of the corresponding instruction. A read only operand coding supplies the data an input of the functional unit. A read/advance operand coding supplies the data and also advances the stream to the next sequential data elements. The read only operand coding permits reuse of data without requiring a register of the register file for temporary storage.

Abstract: A system, method, and device are shown that are operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network by selectably switching bit positions of the input data stream. In some examples, a device includes a first circuit configured to selectably switch bit positions of a first subset of the data stream with a second subset of the data stream and a second circuit configured to: selectably switch bit positions of a first subset of the first subset of the data stream with a second subset of the first subset of the data stream, and selectably switch bit positions of a first subset of the second subset of the data stream with a second subset of the second subset of the data stream.

Abstract: An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.

Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. An element duplication unit optionally duplicates data element an instruction specified number of times. A vector masking unit limits data elements received from the element duplication unit to least significant bits within an instruction specified vector length. If the vector length is less than a stream head register size, the vector masking unit stores all 0's in excess lanes of the stream head register (group duplication disabled) or stores duplicate copies of the least significant bits in excess lanes of the stream head register.

Abstract: An IC manufacturing system including a manufacturing tool having a non-standard communication interface and/or protocol capability, wherein a computer platform of the manufacturing tool is configured with a capture engine operable to monitor operator interactions with the manufacturing tool for facilitating an automated electronic out-of-control action plan (eOCAP) scheme in conjunction with a network-hosted server platform.

Abstract: A differential transceiver including a driver circuit and a receiver circuit, and a serial communications network including the transceiver. The receiver circuit includes an input resistor attenuator, having first and second attenuator inputs coupled to the first and second terminals, respectively, a differential comparator having first and second comparator inputs, and an output buffer having an input coupled to the output of the comparator. The receiver circuit further includes a first switch coupling the first attenuator output to the first comparator input, a second switch coupling the second attenuator output to the second comparator input, and a fail-safe circuit including first and second current sources coupled to the first and second comparator inputs, respectively, and third and fourth switches coupled in series between the first and second current sources.

Abstract: In an example, a system includes an oscillator circuit on a chip. The oscillator circuit includes a charging current generator including a current mirror, an amplifier, and an on-chip resistor, where the on-chip resistor is coupled to a pin on the chip. The oscillator circuit also includes oscillator circuitry coupled to the charging current generator, where the oscillator circuitry includes a comparator, a phase generator, a first capacitor coupled to a first resistor, and a second capacitor coupled to a second resistor. The system also includes an external resistor coupled to the pin, where the external resistor is external to the chip. The system includes an external capacitor coupled to the pin, where the external capacitor is external to the chip.