Abstract: An apparatus includes a substrate, a core, a primary side circuit, first and second secondary side circuits, a primary winding, and first and second secondary windings. The substrate includes first, second, and third metal layers. The core is in the substrate. The primary side circuit, and the first and second secondary side circuits are on the substrate. The primary winding is in the first metal layer of the substrate. The primary winding wraps around the core and is coupled to the primary side circuit. The first secondary winding is in the second metal layer of the substrate. The first secondary winding wraps around the core and is coupled to the first secondary side circuit. The second secondary winding is in the third metal layer of the substrate. The second secondary winding wraps around the core and is coupled to the second secondary side circuit.

Abstract: An example apparatus includes instructions and programmable circuitry configurable to at least one of instantiate or execute the instructions to authenticate a request to update a first trim value to a second trim value, wherein the first trim value is stored in a memory. The example apparatus also includes instructions to, in response to authentication of the request, store the second trim value to the memory while the first trim value remains stored in the memory.

Abstract: A voltage converter includes a power stage, a compensator circuit, and a modulator circuit. The power stage circuit has an input voltage terminal, an output voltage terminal, and a pulse width modulation (PWM) control input. The compensator circuit has a voltage input coupled to the output voltage terminal and has a compensation output. The modulator circuit has a compensation voltage input and a PWM control output. The compensation voltage input is coupled to the compensation output, and the PWM control output is coupled to the PWM control input. The modulator circuit includes a slope compensation ramp generator circuit that is configured to generate a slope compensation voltage ramp having a slope that decreases during at least a portion of a switching cycle.

Abstract: A multi-phase buck-boost converter includes a first half-bridge circuit, a second half-bridge circuit, a third half-bridge circuit, and a control circuit. The first half-bridge circuit is coupled to a first inductor terminal. The second half-bridge circuit is coupled to a second inductor terminal. The third half-bridge circuit is coupled to a third inductor terminal, a system voltage terminal, and a battery terminal. The control circuit is coupled to the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit. The control circuit is configured to transition the first half-bridge circuit, the second half-bridge circuit, and the third half-bridge circuit from operation in a buck mode to operation in a buck-boost mode based on an off-time of the first half-bridge being less than a particular time.

Abstract: One example includes an antenna-on-package (AoP) system. The system includes a first transmission line patterned on a first metal layer. The first metal layer can be arranged to be coupled on a printed circuit board (PCB). The system also includes an antenna portion patterned on a second metal layer. The first and second metal layers can be separated by at least one dielectric layer. The system further includes a coaxial transition portion comprising a via configured to communicatively couple the first transmission line on the first metal layer to a second transmission line on the second metal layer. The second transmission line can be coupled to the antenna portion.

Abstract: An integrated circuit (IC) includes a semiconductor substrate having a first surface and a second surface opposite the first surface. A through wafer trench (TWT) extends from the first surface of the semiconductor substrate to the second surface of the semiconductor substrate. Dielectric material is in the TWT. An interconnect region has layers of dielectric on the first surface of the substrate. The interconnect region has a conductive transmit patch. An antenna is formed, at least in part, by the dielectric material in the TWT and the transmit patch in the interconnect region. The antenna is configured to transmit or receive electromagnetic radiation between the transmit patch and the second surface of the semiconductor substrate through the dielectric material within the trench.

Abstract: One example includes a power supply system. The system includes a power switch configured to activate via a control voltage responsive to a first state of an activation signal to conduct current from a power rail to a switching terminal. The system further includes a power switch deactivation driver configured to control an amplitude of the control voltage responsive to a second state of the activation signal based on a voltage difference between the power rail and the switching terminal to provide for a variable rate of deactivation of the power switch.

Abstract: A method and apparatus of wireless communication between a base station and at least one user equipment. The method includes: transmitting an enhanced physical downlink control channel from the base station to the at least one user equipment using a demodulation reference signal antenna port; transmitting message from the base station to the at least one user equipment which is scheduled by the enhanced physical downlink control channel; receiving the message at the at least one user equipment; determining at the at least one user equipment whether the message was correctly received; and transmitting an ACK/NAK signal on an ACK/NAK resource determined from the enhanced physical downlink control channel from the at least one user equipment to the base station indicating whether the message was correctly received by the at least one user.

Abstract: A technique for method for executing instructions in a processor includes receiving a first instruction, receiving a second instruction, identifying a functional unit specified by an opcode contained in an opcode field of the first instruction, selecting a field of the second instruction that contains predicate information based on the identified functional unit, and executing the first instruction in a conditional manner using the identified functional unit and the predicate information contained in the selected field of the second instruction.

Abstract: An example apparatus includes multiplexer circuitry configured to couple a communication module to at least one of a data bus input or a test signal; and embedded pattern generator (EPG) circuitry coupled to the multiplexer circuitry, the EPG circuitry including: clock divider circuitry including a plurality of clock outputs, the clock divider circuitry configured to be coupled to an output of a clock, the plurality of clock outputs configured to be of a frequency equal to a division of a frequency of the output of the clock; a multiplexer including a multiplexer output, the multiplexer configured to couple one of the plurality of clock outputs to the multiplexer output; and signal generator circuitry including an input clock, an EPG input, and a plurality of data outputs, the input clock coupled to the multiplexer output, the signal generator circuitry configured to generate a data stream.

Abstract: An integrated circuit (IC) including Flash memory and CMOS logic circuitry and a method of fabrication thereof is disclosed. The IC comprises a substrate including a recessed area of a first region, a Flash memory cell gate stack formed in the recessed area, a wordline (WL) transistor formed in the recessed area and coupled with the Flash memory cell gate stack, the WL transistor including a WL gate formed over a first gate oxide layer exclusive of nitridation, and a transistor formed in a second area of the substrate separate from the recessed area, the transistor forming at least a portion of logic circuitry of the IC and including a second gate oxide layer having nitridation.

Abstract: In one example, a controller circuit is configured to: receive a first measurement signal representing a power converter input voltage; receive a second measurement signal representing a power converter output voltage; receive an indication of whether a voltage across a switch is positive during a state change of the switch; based on the first and second measurement signals and the indication, determine: a charging interval; a first dead time interval after the charging interval; a discharging interval; and a second dead time interval after the discharging interval; and provide a first control signal at the first control output, and provide a second control signal at the second control output, in which the states of the first and second control signals vary across the charging interval, the first and second dead time intervals, and the discharging the interval.

Abstract: A first input of a modulator circuit is coupled to a current feedback terminal. An output of the modulator circuit is coupled to an input of a power stage circuit. A first input, a second input, and an output of a voltage compensation circuit are coupled to a voltage feedback terminal, a voltage reference terminal, and a compensation terminal, respectively. A first input of a summing circuit is coupled to the output of the voltage compensation circuit. An output of the summing circuit is coupled to a second input of the modulator circuit. An output of an offset generation circuit is coupled to a second input of the summing circuit. An input of a filter circuit is coupled to the output of the voltage compensation circuit. An output of the filter circuit is coupled to an input of the offset generation circuit.

Abstract: An example apparatus includes: a first metal layer including: a first delay line having a surface area; and a second metal layer including: a second delay line having a surface area overlapping the surface area of the first delay line; and an insulating layer coupled between the first metal layer and the second metal layer.

Abstract: An apparatus includes a first D flip-flop including a first data output, a first negative edge-triggered clock input, and a first reset input, and a second D flip-flop including a second data output, a second negative edge-triggered clock input, and a second reset input. The apparatus includes a logic gate having an output and first and second inputs, the first input of the logic gate coupled to the first data output, and the second input of the logic gate coupled to the second data output, in which the output of the logic gate is configured to be a first clock output of the apparatus. A delay circuit of the apparatus includes an output and input, the output of the delay circuit coupled to the first and second reset inputs, and the input of the delay circuit coupled to the output of the logic gate.

Abstract: In an example, a circuit includes clock data recovery (CDR) circuitry having an input and an output. The circuit also includes a delay circuit having an input coupled to the output of the CDR circuitry, and having an output. The circuit includes a multi-phase oscillator having an input coupled to the output of the delay circuit, and having an output. The circuit also includes a divider having an input coupled to the output of the multi-phase oscillator, and having an output coupled to the input of the CDR circuitry.

Abstract: A CNN based-signal processing includes receiving of an encrypted output from a first layer of a multi-layer CNN data. The received encrypted output is subsequently decrypted to form a decrypted input to a second layer of the multi-layer CNN data. A convolution of the decrypted input with a corresponding decrypted weight may generate a second layer output, which may be encrypted and used as an encrypted input to a third layer of the multi-layer CNN data.

Abstract: An apparatus includes: a first conductor layer patterned into parallel strips having a first end and an opposite second end formed on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers extending through the dielectric material; a second conductor layer in the multilayer package substrate spaced from the first conductor layer, the second conductor layer patterned into parallel strips having a first end and a second end, the second conductor layer coupled to the first conductor layer by vertical connectors formed of the conductive vertical connection layers at the first end and the second end, and a semiconductor die mounted to the device side surface of the multilayer package substrate that is spaced from and coupled to the second conductor.

Abstract: In one example, an integrated circuit comprises a transistor and a metal layer. The transistor has an insulator layer over a substrate that includes gallium nitride (GaN). First and second opening in the insulator layer respectively define a drain region and a source region of the transistor. A gate electrode extends into the insulator layer between the source region and the drain region. The metal layer includes a drain via and a source via. The drain via extends through the first opening to the drain region. The source via extends through the second opening to the source region. A source field plate is in the metal layer. The source field plate extends over the gate electrode and provides a contiguous electrically conductive path to the source region.

Abstract: In an advanced driver-assistance system (ADAS), RAW sensor image processing for a machine vision (MV) application is important. Due to different color, e.g., red/green/blue (RGB), color components, being focused by the lens at different locations in image plane, the lateral chromatic aberration phenomenon may sometimes be observed, which causes false color around edges in the final image output, especially for high contrast edges, which can impede MV applications. Disclosed herein are low-latency, efficient, optimized designs for chromatic aberration correction (CAC) components.