Abstract: A semiconductor memory device having a MOS transistor with a floating gate capable of storing data.The MOS transistor has an erase gate which overlaps part of the floating gate with an insulating film interposed therebetween. Upon application of a high voltage on the erase gate, the field emission is caused between the floating gate and the erase gate and the charge stored on the floating gate is removed.

Abstract: A matrix logic circuit network comprises a great number of interconnected logic gates. Input and output lines of the logic gates are arranged in the matrix array. By rearranging the input and output lines of the matrix in accordance with a sort algorithm, direct connection points of the input and output lines to which the same signals are allotted and connecting elements forming logic gates located at given intersections of the input and output lines are arranged within a diagonal area with a limited width, which extends along a diagonal line of the matrix.

Abstract: A semiconductor device having a semiconductor substrate, wherein first and second insulating gate FET transistor connected respectively, in series with first and second polycrystalline silicon layers acting as loads of first and second inverters are formed. The first polycrystalline silicon layer is provided above a gate electrode of the second insulation gate FET transistor, and the second polycrystalline silicon layer is provided above a gate electrode of the first insulation gate FET transistor.

Abstract: A nickel-chromium alloy with addition of silver used for ornamental purposes, such as for spectacles frames wherein silver particles of the alloy are arrayed in lines in substantially one direction. The average ratio of the longitudinal distance and width of the line is preferably more than 10.

Abstract: A method for forming a highly precise resist pattern with good reproducibility has the steps of: applying a resist material to a substrate to form a resist film; baking the resist film; cooling the resist film in a controlled manner; selectively irradiating the resist film with one of electromagnetic waves in a predetermined wavelength range and particle beam having predetermined energy; and developing the resist film to form a resist pattern.

Abstract: For the purpose of compensating for geometric errors at four corners of a color picture there are provided a circuit for separating a vertical scanning saw tooth shaped signal into first and second signals corresponding to fore and rear portions of a vertical scanning period, first and second balanced modulators respectively modulating a horizontal scanning saw tooth shaped signal in accordance with the separate first and second signals, circuits for separating the outputs of the modulators in accordance with their reference levels, and circuits for generating geometric error compensation outputs corresponding to specific portions in the horizontal and vertical directions of the scanned picture.

Abstract: A semiconductor device comprising a semiconductor substrate with at least one semiconductor region formed in it, a polycrystalline silicon layer formed in contact with the semiconductor region and a metal layer formed on the polycrystalline silicon layer. The peripheral portion and outer edges of the polycrystalline silicon layer are covered with an insulation layer.

Abstract: A semiconductor circuit has a power source terminal set at a positive potential, a reference potential terminal set at a reference potential, a first MOS transistor whose current path is connected between the power source terminal and an output terminal, and a second MOS transistor whose current path is connected between the output terminal and the reference potential terminal. The gates of the first and second MOS transistors are commonly connected to an input terminal. The first and second MOS transistors are respectively n- and p-channel MOS transistors.

Abstract: An input protection device for a C-MOS device having an n-type semiconductor substrate and a p-type well region. The device comprises a diode consisting of the p-type well region and an n.sup.+ -type layer diffusion formed in the p-type well region and connected between a gate of a C-MOS FET and ground. The n.sup.+ -type layer of the diode has a higher impurity concentration and a greater diffusion depth than those of n.sup.+ -type layers formed in the p-type well region and constitute the source and drain of an n-channel MOSFET.

Abstract: A video RAM write control circuit has a video RAM for storing pattern data of one frame at addresses thereof which correspond to display positions, and a control circuit for generating write pattern data and write addresses. The video RAM stores a pattern which is continuous in the horizontal direction, at consecutive addresses thereof. Each row on the screen consists of several rasters. A video RAM address has a memory address representing a position in the horizontal direction, in its lower bits, so well as a raster address representing a raster position of the row, at upper bits thereof. A write address is rotated toward the MSB by the number of bits of the raster address, and a resultant permuted address is supplied to the video RAM.

Abstract: A semiconductor device has a passivation layer including a polyimide film. Argon ions are implanted in the polyimide film to convert it into an electrically stable insulating film.

Abstract: In a nuclear magnetic resonance (NMR) diagnostic apparatus, the NMR signals from a portion of an object excited repeatedly by the same type excitation pulses are temporarily stored and the signal-to-noise (S/N) ratio thereof is improved by summing together at least two cos signal components, or two sin signal components of the NMR signals which were taken during these examination periods. An image processing circuit is used to process the NMR signals with impioned S/N ratio so as to obtain a tomographic image of the object.

Abstract: An interface circuit can assign a common input/output port address to a plurality of I/O circuits. Each common I/O port is defined in terms of pages. In an actual data input/output, a specific port address is used for port control so as to select one common page. The interface circuit has a first decoder for decoding a specific port address signal. The interface circuit also had a data setter for setting data supplied from a specific bit line of the data bus. The data is set in the data setter in accordance with the decoded signal from the first decoder. Each of the plurality of I/O circuits has a second decoder for decoding the common I/O port address signal. An output from the setter enables a corresponding one of second decoders. As a result, a specific page is selected.

Abstract: A laminated body comprising a ceramic member and a metal member, and a method of forming the laminated body are described. The laminated body is characterized in that the ceramic member contains in its surface portion a bonding agent and the metal member is directly bonded to the surface of the ceramic member. The method of forming the laminated body is characterized in that a bonding agent-containing layer is first formed in the surface of the ceramic member and then the bonding agent-containing layer is heated while being contacted with the metal member.

Abstract: A voltage comparator circuit that is useful in A/D converters and D/A converters. The circuit comprises a comparison capacitor, a holding capacitor and input switching transistors. The holding capacitor holds the comparison voltage applied to it from the input switching transistors through the comparison capacitor. Therefore, the circuit can perform accurate voltage comparison even if the input voltages are sampled at a high sampling frequency.

Abstract: A character data processor for a videotex or teletext system includes a microcomputer section, a self data processing unit and a read/write memory. A memory access period for the memory exists in one read/write cycle of character data packets. Data processing unit responds to a first pulse indicating the start of the memory access period and to a second pulse indicating the end of the memory access period. Data processing unit includes an address change circuit which stores initial address data and transfers address data stored therein to the memory according to a transfer pulse. The content of address data is changed by a change pulse. A data register relays data transferred between the microcomputer section and the memory. A generator circuit generates the transfer pulse, the change pulse and a clock pulse according to the generation of the first and second pulses and a detection signal. A detection circuit responds to prescribed data indicating the run length of character data.

Abstract: A radiation-sensitive carrier body directly utilized as a stamper has a glass substrate, a first highly adhesive layer securely adhered to the substrate, a radiation-sensitive layer which discharges a gas component upon being irradiated with a laser beam and which locally forms a protuberance due to the absorbed energy, a second highly adhesive layer securely adhered to the specific material of the radiation-sensitive layer and which deforms in accordance with deformation of the layer, and a metal layer which has a high releasability to allow easy separation from a optical disk substrate material such as an acrylic material when the carrier body is used as a stamper substrate for manufacturing optical disks. A protuberance formed on the carrier body such as a continuous spiral protuberance allows formation of a corresponding spiral groove in the acrylic material, serving as a pre-track into which desired information will be digitally written by a user.

Abstract: In an image forming apparatus according to the present invention, a cleaning device which allows for the repeated use of the photosensitive drum is removed from a space between a transferring device for transferring a visible image to the transfer sheet and a charging device for charging the photosensitive drum. The cleaning device is omitted from the image forming apparatus and a developing device for developing an electrostatic latent image can also serve as the cleaning device. Alternatively, the cleaning device is disposed between the charging device and the developing device.

Abstract: A computer system for preventing copying or duplication of a program which has a CPU, a ROM, a RAM, an FDD unit, a loader program executed by the CPU for loading the program from the FDD unit to the memory, an address selector switch, and an FM/MFM modulating circuit. The CPU reads the program from the FDD unit to the RAM under the control of a control program stored in the ROM, the program being stored in the FDD unit in the MFM mode which does not allow readout of the program by the loader program. The readout program is modified by the FM/MFM modulating circuit in accordance with a machine number unique to the machine and read from the address selector switch. The modified program is written in the FDD unit by the FM/MFM modulating circuit.

Abstract: In the optical memory device of this invention, an annular information recording area is formed on one surface of a disc-shaped subplate which is rotatable about a center hole. Information is recorded on, or read from, the circular or spiral track of the information recording area, the track being centered on the center hole. On the same surface of the subplate is formed a position signal area of the same material as that of the information recording area, but at a different position from the information recording area. As the device is rotated, the time when the position signal area passes a given point may be detected and used as a reference, so that the location within the track of recording or reproducing information can be determined.