Patents Assigned to Tokyo Shibaura Denki Kabushiki Kaisha
  • Patent number: 4734267
    Abstract: An apparatus for growing compound semiconductor single crystals includes a collector which removes the excess amount of melt B.sub.2 O.sub.3 from the crucible containing melt GaP and melt B.sub.2 O.sub.3.The collector moves up and down independently with reference to the shaft used in pulling the single crystals from the crucible.
    Type: Grant
    Filed: July 6, 1983
    Date of Patent: March 29, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Masakatu Kojima
  • Patent number: 4734849
    Abstract: In a one-chip high density arithmetic control unit capable of prefetching user's instructions from main memory, an arithmetic logic unit (ALU) subtracts the contents of a location counter holding the address of the next instruction to be executed, from the contents of a memory address register holding an address into which data will be written. The difference is fed through the gates connected to the ALU for determining whether or not prefetched instructions will have to be refetched. An address matching mechanism provided outside the one-chip arithmetic control unit includes a comparator for comparing memory addresses to a preset execution stop address.
    Type: Grant
    Filed: July 16, 1986
    Date of Patent: March 29, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tsuneo Kinoshita, Fumitaka Sato, Isamu Yamazaki
  • Patent number: 4732872
    Abstract: The invention provides a method for making a semiconductor device including a bipolar transistor and a capacitor. An oxide film and a silicon nitride film are formed and patterned on a semiconductor substrate. A layer of polycrystalline silicon or of metal silicide containing an impurity is formed between an emitter electrode and an emitter region of the transistor and between an electrode and a thin oxide film of the capacitor. The doped polycrystalline silicon or metal silicide is then patterned to form a barrier layer protecting the oxide film and an intermediate layer acting as a diffusion source to the underlying substrate.
    Type: Grant
    Filed: June 26, 1985
    Date of Patent: March 22, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Shigeru Komatsu
  • Patent number: 4731725
    Abstract: A data processing system for use in a total medical image diagnosis comprising a central processing unit, a first memory connected to the central processing unit for storing a plurality of types of fundamental data used for constructing a decision tree, a second memory connected to the central processing unit for storing various programs for constructing the decision tree, first data input system for inputting the fundamental data and the programs stored in the first and second memories into the central processing unit, circuitry for storing output data from the central processing unit and converting the output data into a bright signal for a display medical image, displaying for displaying a medical image corresponding to the bright signal from the storing and converting circuitry, a light pen connected to the central processing unit and operated by an operator for inputting a portion of the fundamental data displayed on the displaying means into the central processing unit as selected by the operator to con
    Type: Grant
    Filed: September 18, 1986
    Date of Patent: March 15, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yasuzo Suto, Katsuyoshi Saito, Kenichi Sato
  • Patent number: 4728823
    Abstract: A logic circuit on a substrate is switchable between a test mode and an operational mode. First and second NOR gates are cross-coupled and may be switched between an operational mode and a test mode by the application of a control signal to first and second transfer gates coupled to the inputs of the NOR gates. The first NOR gate includes a p-type region and an n-type region formed in said substrate and traversed with first and second conductive layers insulated from the p and n-type regions. Thus, the first NOR gate includes two p-channel transistors and two n-channel transistors. The second NOR gate is also formed by a p-type region and an n-type region traversed with third and fourth conductive layers. Thus, the second NOR gate also includes two p-channel transistors and two n-channel transistors. The transfer gates are located on the substrate between the first and second NOR gates.
    Type: Grant
    Filed: July 22, 1986
    Date of Patent: March 1, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Tsuneo Kinoshita
  • Patent number: 4727589
    Abstract: A plurality of picture data storage/retrieval apparatuses are connected to each other through a communication line. Each picture data storage/retrieval apparatus has a two-dimensional scanning device for inputting picture data, a keyboard for entering control data, an optical disk for storing the picture data input through the two-dimensional scanning device, a floppy disk for storing a control program, a CRT display device for displaying the picture data stored in the optical disk, a printer for producing a hard copy of the picture data stored in the optical disk, and a communication control unit. When a given apparatus desires registration, retrieval or deletion of picture data in another apparatus, a control unit of the given apparatus communicates with the another apparatus through the communication control units.
    Type: Grant
    Filed: October 9, 1986
    Date of Patent: February 23, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kenji Hirose, Akira Hamade
  • Patent number: 4727282
    Abstract: A color cathode-ray tube is disclosed, which has a shadow mask facing the face plate inner surface and having slit apertures formed in a predetermined arrangement. The center-to-center distance or interval Px of the slit apertures on the horizontal axis increases as a first function along the horizontal axis from the center of the shadow mask to the periphery region thereof. The center-to-center distance or interval Sx in peripheral regions of the shadow mask remotest from the horizontal axis increases as a second function different from the first function along the horizontal axis from the vertical axis to the periphery region thereof. The first and second functions representing the respective slit aperture intervals Px and Sx are given as ##EQU1## where X is 1, 2, 3, . . . , and .alpha. and .beta. are .alpha.<3 and .beta..ltoreq.6.
    Type: Grant
    Filed: July 23, 1986
    Date of Patent: February 23, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kiyoshi Tokita, Michio Nakamura
  • Patent number: 4726160
    Abstract: An electric refrigerator is disclosed which includes first and second coolers independently disposed in a freezer and a refrigeration chamber, respectively, a compressor for delivering a refrigerant therefrom, an electromagnetic valve for switching a refrigerant channel including the first and second coolers between a first referigerant flow path for supplying the refrigerant to only the first cooler and a second refrigerant flow path for supplying the refrigerant to both the first and second coolers, and a control circuit for causing the electromagnetic valve to form the first refrigerant flow path for a predetermined time interval and for causing the electromagnetic valve to form the second refrigerant flow path by preventing interruption of the compressor when the predetermined time interval has elapsed and an air temperature in the refrigeration chamber is higehr than a predetermined temperature.
    Type: Grant
    Filed: June 28, 1983
    Date of Patent: February 23, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Syunro Kawaguchi, Hiroshi Tamura, Yasuhiro Ogita
  • Patent number: 4727363
    Abstract: A video RAM write control apparatus cmprises a video RAM of byte access for storing dot pattern data, and a write circuit for supplying write data of one byte and a write enable signal to the video RAM. The video RAM includes n (n being an arbitrary natural number) memory blocks, each consisting of 1 bit.times.N addresses, the same address being assigned to the n-bits word. The write circuit includes a bit mask register in which an n-bit bit mask pattern data having a flag in a specific bit is set, and NAND gates for supplying AND signals of an output of each bit of the bit mask register and a write enable signal to the write enable terminal of each memory block.
    Type: Grant
    Filed: September 29, 1986
    Date of Patent: February 23, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Takatoshi Ishii
  • Patent number: 4727395
    Abstract: In an image forming apparatus according to the present invention, a cleaning device which allows for the repeated use of a photosensitive drum is removed from a space between a transferring device for transferring a visible image to the transfer sheet and a charging device for charging the photosensitive drum. The cleaning device is omitted from the image forming apparatus and a developing device for developing an electrostatic latent image can also serve as the cleaning device. Alternatively, the cleaning device is disposed between the charging device and the developing device.
    Type: Grant
    Filed: November 19, 1986
    Date of Patent: February 23, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Goro Oda, Haruhiko Ishida
  • Patent number: 4723155
    Abstract: A fuse element is formed on a field insulation film on a semiconductor substrate of n conductivity type in which MOS transistors are formed. A first guard ring region of second conductivity type is provided in the substrate, surrounding the semiconductor substrate region under the fuse element. A second guard ring region of first conductivity type is formed in the substrate, surrounding the first guard ring region. Proper potentials are applied to the first and second guard ring regions.
    Type: Grant
    Filed: September 24, 1986
    Date of Patent: February 2, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Yukimasa Uchida
  • Patent number: 4722443
    Abstract: An apparatus for processing paper sheets comprises a batch feeder for carrying the withdrawn paper sheets, a takeout device for picking up the paper sheets from the batch feeder, one by one, an inspection section for inspecting the paper sheets picked up by the takeout device, whereby the paper sheets are classified into two groups, an unmachinable first group and a machinable second group, a first collecting device for collecting the first group of paper sheets, and a judgment unit for classifying the second group of paper sheets into two subgroups, a legitimate third group and a counterfeit fourth group. The first collecting device includes a second collecting device for collecting the third group of paper sheets, and third collecting device for collecting the fourth group of paper sheets.
    Type: Grant
    Filed: April 30, 1986
    Date of Patent: February 2, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Nobusato Maruyama, Takeshi Kohno, Kazuhito Haruki, Kozo Matsumoto, Toshiyuki Miyano
  • Patent number: 4720846
    Abstract: An automatic telephone answering and recording apparatus having recording means for recording an incoming message sent by a caller over a telephone line on a first recording medium; a speaking circuit; first means responsive to a call signal sent by the caller for operating to connect the speaking circuit to the telephone line associated with the caller; second means responsive to the first means for transmitting an answering message previously recorded on a second recording over the telephone line to the caller; detecting means responsive to an ending of the answering message for detecting the state of the recording means to determine whether it is ready to record an incoming message; and transmitting means responsive to the detecting means for transmitting to the caller a first aural synthesis output identifying the state of the recording means.
    Type: Grant
    Filed: August 1, 1983
    Date of Patent: January 19, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Motoichi Hattori
  • Patent number: 4717645
    Abstract: A method for forming a highly precise resist pattern with good reproducibility has the steps of: applying a resist material to a substrate to form a resist film; baking the resist film; cooling the resist film in a controlled manner; selectively irradiating the resist film with one of the electromagnetic waves in a predetermined wavelength range and particle beam having predetermined energy; and developing the resist film to form a resist pattern.
    Type: Grant
    Filed: October 22, 1985
    Date of Patent: January 5, 1988
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yoshihide Kato, Kei Kirita, Toshiaki Shinozaki, Fumiaki Shigemitsu, Kinya Usuda, Takashi Tsuchiya
  • Patent number: 4716308
    Abstract: A MOS logic circuit comprises two P channel MOSFETs connected in parallel between a positive power source V.sub.DD and a logic signal output terminal and two series circuits connected in parallel between a ground voltage source V.sub.SS and the terminal, each series circuit being comprised of serially connected two N channel MOSFETs. The gate electrodes of the MOSFETs located in the corresponding positions in the respective series circuits are connected to first and second logic signal input terminals, respectively. Similarly, the gate electrodes of the other MOSFETs located in the corresponding positions in the respective series circuits are connected to the second and first logic signal input terminals, respectively.
    Type: Grant
    Filed: July 29, 1983
    Date of Patent: December 29, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Kenji Matsuo, Itsuo Sasaki, Hiroaki Suzuki, Mitsuyuki Kunieda
  • Patent number: 4716558
    Abstract: A record disc reproducing apparatus determines the magnitude and polarity of the difference between a preselected data address and a current data address and moves a pickup assembly in a direction to reduce that difference until it drops below a prescribed address tolerance. The amount of movement can either be a given distance or some fraction either of the difference between the current and prescribed data addresses, or of the breadth of a program portion.
    Type: Grant
    Filed: December 27, 1983
    Date of Patent: December 29, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Yoshitaka Katayama, Daiki Nabeshima, Shinichi Nakamura
  • Patent number: 4714668
    Abstract: A method for patterning a layer having a high reflectance includes directly forming on a layer having a high reflectance a light-absorbing film having a ratio of transmitted light intensity to exposing incident light intensity of not more than 30% and forming a photosensitive material film on the light-absorbing film. A selected region of the photosensitive material film is irradiated with the exposing incident light, and the photosensitive material film is developed to form a first pattern. The light-absorbing film is selectively etched using the first pattern as a mask so as to form a second pattern. Finally, the layer having the high reflectance is selectively etched using the second pattern as a mask.
    Type: Grant
    Filed: June 24, 1986
    Date of Patent: December 22, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Tsunehisa Uneno, Yutaka Kamata, Sinji Miyazaki
  • Patent number: 4713789
    Abstract: To process X-ray transmission image data at a high speed, a processor comprises a memory section including at least first, second and third storage, the first storage storing the X-ray transmission image data in a digital form which is used for medical diagnosis, and the second and third storage storing temporarily and exclusively the processed image data. The processor also includes a processor control section including, at least first, second and third address generators each of which independently generates an address signal and applies the same to the corresponding storage respectively, processing circuit which receives the image data and image data which is temporarily stored in one of the second and third storage and processes both image data and applies the same for storage purposes to the remaining of the second and third storage.
    Type: Grant
    Filed: October 26, 1983
    Date of Patent: December 15, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Kaoru Suzuki
  • Patent number: 4713302
    Abstract: A sintered ceramic body has a surface layer containing yttrium silicate, cristobalite and silicon nitride, and mainly consists of silicon nitride. The silicon ceramic body is manufactured by preparing a composition containing a silicon nitride powder and an yttrium oxide powder, forming and sintering the composition, and heat-treating the sintered body in an oxidizing atmosphere. The ceramic body has a high mechanical strength over its entire surface and has little variation in mechanical strength.
    Type: Grant
    Filed: April 30, 1986
    Date of Patent: December 15, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Michiyasu Komatsu
  • Patent number: 4708680
    Abstract: A color picture tube comprises a shadow mask which is formed to, oppose at a small gap therefrom, a phosphor screen formed on the inner surface of a panel. The shadow mask comprises a sheet of a nickel-containing iron alloy which contains 0.1% by weight or less of manganese and having an austenite grain number of 7 or less both within and at surfaces of the sheet, the austenite grain number being defined by JIS G 0551 of the Japanese Industrial Standards. The iron alloy sheet is annealed in a vacuum of 10.sup.-1 Torr or less at a temperature of 1,000.degree. C. or higher prior to formation into the shadow mask.
    Type: Grant
    Filed: January 13, 1986
    Date of Patent: November 24, 1987
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Masaharu Kanto, Eiichi Akiyoshi, Yasuhisa Ohtake