Patents Assigned to TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
  • Patent number: 11600292
    Abstract: According to one embodiment, a magnetic disk device comprises a magnetic disk, a magnetic head, a monitoring unit, and a control unit. When carrying out write of data to a first track, if an absolute difference between a light output monitored by the monitoring unit at the time of write and a light output monitored last time by the monitoring unit exceeds a predetermined value, the control unit controls a position of a write head and writes data again to the first track or a second track one track before the first track.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: March 7, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takuya Matsumoto, Yusuke Tomoda
  • Patent number: 11600692
    Abstract: According to one embodiment, a semiconductor device has a cell region and an end region adjacent to the cell region in a first direction and surrounding the cell region. A first semiconductor layer of a first conductivity type is in the cell region and the end region. Guard rings of a second conductivity type are at a first surface in the end region. The guard rings surround the cell region. An insulating film is on the first surface in the end region. Conductive members are on the insulating film and separated from the guard rings in a second direction. A first conductive member has a cell-region-side edge above a central portion of a first guard ring. The first guard ring has an end-region-side edge below a central portion of the first conductive member.
    Type: Grant
    Filed: March 1, 2021
    Date of Patent: March 7, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Sozo Kanie, Hiroshi Kono
  • Patent number: 11600993
    Abstract: According to one embodiment, a semiconductor protection circuit includes a first MOS transistor that has a drain that is connected to an input terminal, a source that is connected to an output terminal, and a gate that is connected to a control terminal, a second MOS transistor that has a drain that is connected to the gate of the first MOS transistor and a source that is connected to the source of the first MOS transistor, a rectifier element that is connected in a forward direction from a gate of the second MOS transistor to the gate of the first MOS transistor, and a low-pass filter that is connected between the gate and the source of the second MOS transistor.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: March 7, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Chen Kong Teh
  • Patent number: 11600347
    Abstract: According to an embodiment, a storage device includes a plurality of storage elements, a plurality of readout circuits, and a delay circuit. The readout circuits include a first readout circuit and a second readout circuit different from the first readout circuit. The readout circuits each determines data stored in a corresponding one of the storage elements and outputs a result of the determination, in response to receipt of an activation signal. The delay circuit is connected at a first end to the first readout circuit and connected at a second end to the second readout circuit. The delay circuit supplies the activation signal to the second readout circuit with a time interval after supplying the activation signal to the first readout circuit.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: March 7, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Toshiaki Dozaka
  • Patent number: 11601108
    Abstract: According to one embodiment, in an isolator, a first capacitive element is arranged on a first signal line. The first capacitive element has one end electrically connected to an input side circuit and having another end electrically connected to an output side circuit. A second capacitive element is arranged on a second signal line. The second capacitive element having one end electrically connected to the input side circuit and having another end electrically connected to the output side circuit. A first inductive element has one end electrically connected to a first node between the first capacitive element in the first signal line and the output side circuit. A second inductive element has one end electrically connected to a second node between the second capacitive element in the second signal line and the output side circuit.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: March 7, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yuichi Sawahara
  • Patent number: 11600298
    Abstract: According to one embodiment, a disk device includes a recording medium, a magnetic head, a ramp, and an actuator. The recording medium has a recording surface and is rotatable around a first rotation axis. The actuator includes a first portion extending so as to be separated from a second rotation axis and separated from the recording surface as the distance from the second rotation axis increases, holds the magnetic head, and is rotatable around the second rotation axis. A first support is provided on the ramp, extends around the second rotation axis, and can support the first portion so that the magnetic head is separated from the recording surface. A second support is provided on the ramp, is located between the first rotation axis and the first support, is separated from the second rotation axis farther than the first support, and can support the first portion.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 7, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yasuhiko Kato
  • Publication number: 20230062839
    Abstract: According to one embodiment, a magnetic head includes a magnetic pole, a shield, and a non-magnetic layer. The non-magnetic layer is provided between the magnetic pole and the shield. The non-magnetic layer is in contact with the magnetic pole and the shield. The non-magnetic layer includes a first element including at least one selected from the group consisting of Cu, Au, Cr, V, Al and Ag.
    Type: Application
    Filed: January 27, 2022
    Publication date: March 2, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yuji NAKAGAWA, Masayuki TAKAGISHI, Naoyuki NARITA, Tazumi NAGASAWA, Tomoyuki MAEDA
  • Patent number: 11594476
    Abstract: A semiconductor device includes: a first chip including first and second electrodes provided at a first surface, and a third electrode provided at a second surface positioned at a side opposite to the first surface; a second chip including fourth and fifth electrodes provided at a third surface, and a sixth electrode provided at a fourth surface positioned at a side opposite to the third surface, wherein the second chip is disposed to cause the third surface to face the first surface; a first connector disposed between the first electrode and the fourth electrode and connected to the first and fourth electrodes; and a second connector disposed between the second electrode and the fifth electrode and connected to the second and fifth electrodes.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: February 28, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tatsuya Ohguro, Hideharu Kojima
  • Patent number: 11594250
    Abstract: According to one embodiment, a magnetic disk device includes a disk having a first region in which a plurality of tracks is written and a second region that is positioned with a gap in a first direction of the radial direction of the first region, and in which a plurality of tracks is overwritten in the first direction, a head, and a controller that offsets part of a plurality of tracks which is overwritten in the second region in a second direction opposite the first direction to perform rewriting.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: February 28, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yusuke Tomoda, Akihiko Takeo
  • Patent number: 11594963
    Abstract: According to one embodiment, a switching power circuit compares a reference voltage with a feedback voltage of an output voltage, and controls the output voltage in accordance with the reference voltage, in which in a case where the output current is greater than a predetermined set current, the voltage of the reference voltage is decreased.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: February 28, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Toshimasa Namekawa, Ryoma Matsuo, Katsumasa Tanaka
  • Patent number: 11594530
    Abstract: An eighth semiconductor portion is provided between the first semiconductor portion and the third semiconductor portion. The eighth semiconductor portion is of the second conductivity type, contacting the first semiconductor portion, and having a lower second-conductivity-type impurity concentration than the second semiconductor portion.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 28, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Hideaki Sai
  • Patent number: 11594622
    Abstract: A semiconductor device includes a semiconductor part having a first surface and a second surface opposite to the first surface, a first electrode on the first surface, a second electrode on the second surface, first to third control electrodes between the first electrode and the semiconductor part. The first to third control electrodes are biased independently from each other. The semiconductor part includes a first layer of a first-conductivity-type, a second layer of a second-conductivity-type, a third layer of the first-conductivity-type and the fourth layer of the second-conductivity-type. The second layer is provided between the first layer and the first electrode. The third layer is selectively provided between the second layer and the first electrode. The fourth layer is provided between the first layer and the second electrode. The second layer opposes the first to third control electrode with insulating films interposed.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: February 28, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa
  • Patent number: 11595029
    Abstract: A switch circuit of an embodiment includes a high frequency switch, a first charge pump circuit, a boost signal generation circuit, and a second charge pump circuit. The high frequency switch switches transmission and reception of a high frequency signal. The first charge pump circuit generates a first voltage and a second voltage biased to the high frequency switch. When an edge of an input signal is detected, the boost signal generation circuit generates a first boost signal for temporarily increasing drive capacity of the first charge pump circuit. When the first boost signal is input, the second charge pump circuit operates to temporarily increase the drive capacity of the first charge pump circuit.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 28, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Satoshi Kurachi
  • Patent number: 11594248
    Abstract: The disk device according to one embodiment includes magnetic disks, a magnetic head, a ramp, and a suspension. The suspension includes a sliding portion provided on a load beam. The suspension rotates about a second rotation axis between a load position and an unload position. The ramp includes a wall and a protrusion. The wall has a first support surface that supports the sliding portion when the suspension is located in the unload position. The protrusion includes a second support surface and an intermediate portion. The second support surface faces the magnetic head when the suspension is located in the unload position. The intermediate portion is located between the wall and the second support surface. The intermediate portion includes a first portion and a second portion. The second portion is located between the first portion and the first support surface in the radial direction of the second rotation axis.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 28, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Sinji Tukada
  • Patent number: 11594246
    Abstract: According to one embodiment, a disk device includes a plurality of recording media, a plurality of magnetic heads, a plurality of blades, and a housing. The recording medium has a recording surface, is rotatable around a rotation axis extending in an axial direction intersecting the recording surface, and is aligned in the axial direction. The magnetic head is configured to read and write information from and to the plurality of recording media. The plurality of first blades forms a spoiler, and the first blades of the plurality are located in a plurality of gaps provided between the plurality of recording media. The housing is provided with an inner chamber in which the plurality of recording media, the plurality of magnetic heads, and the plurality of first blades are accommodated. The number of first blades is smaller than the number of gaps.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: February 28, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Sinji Tukada
  • Patent number: 11594251
    Abstract: According to one embodiment, a disk device includes a disk-shaped recording medium, a base accommodating the recording medium, the base including a bottom wall, a sidewall on a peripheral portion of the bottom wall, and a rib on a part of an upper surface of the sidewall and extending along an entire circumference of the sidewall, a first cover on a part of the upper surface of the sidewall, and a second cover on a first surface of the rib and above the first cover. The rib includes a first region with a first width, a second region with a second width less than the first width, and the first surface with a fixed width around an entire circumference of the rib. The first region and the second region are located corresponding to a side portion of the recording medium.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: February 28, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yasuhiko Kato
  • Patent number: 11588475
    Abstract: A semiconductor integrated circuit includes a clock controller generating a clock; and a plurality of blocks that operate by using the clock. The clock controller performs statistical processing for the plurality of blocks, controls a frequency of the clock to a first frequency, changes the frequency of the clock from the first frequency to a second frequency, generates the clock of the second frequency after a time predicted by the statistical processing as a time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed, and supplies the generated clock to the blocks. The clock controller generates a third frequency clock obtained by decimating down the second frequency from the first frequency according to a time for which the first and second frequencies are to be continued after the frequency of the clock is changed from the second frequency to the first frequency, and supplies the generated clock to the blocks.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: February 21, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Haruya Iwata, Tatsuya Tokue, Sohei Kushida, Takayuki Mori, Satoshi Kamiya
  • Patent number: 11588486
    Abstract: According to one embodiment, a bus buffer circuit includes an input buffer circuit that receives an input signal, and outputs a non-inversion input signal and an inversion input signal, a voltage conversion circuit that operates by a second power supply, performs voltage conversion on the non-inversion input signal and the inversion input signal input thereto, and outputs the signals as a voltage-converted non-inversion output signal and a voltage-converted inversion output signal, an output retaining circuit that retains the voltage-converted non-inversion output signal and the voltage-converted inversion output signal at a same potential level when an output enable signal is in a disable state, a determinator that determines whether these signals are at a same potential level, a three-state output buffer circuit that outputs the voltage-converted non-inversion output signal or the voltage-converted inversion output signal from an output terminal, and an output controller that sets the three-state output buf
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 21, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Masaru Mizuta
  • Patent number: 11587840
    Abstract: Provided is a semiconductor device including: a substrate; an electrode layer provided on the substrate; a semiconductor chip being provided on the electrode layer, including a first side surface portion having a first angle with respect to a substrate surface of the substrate, and including a second side surface portion being provided below the first side surface portion and having a second angle smaller than the first angle with respect to the substrate surface; and a resin being provided around the electrode layer and the semiconductor chip and being in contact with the first side surface portion and the second side surface portion.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: February 21, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Hideyuki Yamauchi
  • Publication number: 20230046560
    Abstract: According to one embodiment, a nitride semiconductor includes a base body, a nitride member, and an intermediate region provided between the base body and the nitride member. The nitride member includes a first nitride region including Alx1Ga1-x1N (0<x1?1), and a second nitride region including Alx2Ga1-x2N (0?x2<1, x2<x1). The first nitride region is between the intermediate region and the second nitride region. The intermediate region includes nitrogen and carbon. A concentration of carbon in the intermediate region is not less than 1.5×1019/cm3 and not more than 6×1020/cm3.
    Type: Application
    Filed: February 10, 2022
    Publication date: February 16, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Toshiki HIKOSAKA, Hajime NAGO, Jumpei TAJIMA, Shinya NUNOUE