Patents Assigned to TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
  • Patent number: 11652583
    Abstract: An electronic communication device includes a controller which controls, according to the number of bit data in which an error has occurred of packet data transferred in serial communication, whether to start logging of information about the error of the packet data or stop logging of information about the error of the packet data.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: May 16, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Nobuhiro Ashizuka, Kenji Yoshida
  • Patent number: 11646056
    Abstract: A disk device according to one embodiment includes a recording medium, a magnetic head, a wiring member, and a flexible printed circuit board. The magnetic head is configured to read/write information from/to the recording medium. The wiring member includes a plurality of first terminals, and a plurality of first wires that electrically connect the magnetic head to the first terminals. The flexible printed circuit board includes a surface, a plurality of second terminals located on the surface to be connected to the first terminals by means of a conductive adhesive, and a ground plane spaced apart from the second terminals in a direction along the surface.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: May 9, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Yuki Sato
  • Patent number: 11646051
    Abstract: According to one embodiment, a magnetic disk device includes a disk that includes a first track, a head that includes a heater, writes data to the disk, and reads data from the disk, and a controller configured to set a variation of a parameter related to a write process for the disk within one round of the first track to suppress a variation of an evaluation index corresponding to a write/read processing characteristic within one round of the first track.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: May 9, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroshi Isokawa, Nobuhiro Maeto
  • Patent number: 11646250
    Abstract: A semiconductor device includes metal connector plate having a first lower surface, facing an electrode of a semiconductor chip, a first end surface, a second end surface, and a second lower surface connecting the first end surface and the second end surface. In a first direction parallel to the semiconductor chip, an end surface of the electrode is located between the positions of the first end surface and the second end surface. A distance from the second lower surface to the electrode is greater than a distance from the first lower surface to the electrode. A joining component has a first portion between the first lower surface and the electrode and a second portion between the second lower surface and the electrode.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: May 9, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Daisuke Inoue
  • Publication number: 20230138962
    Abstract: According to one embodiment, a nitride semiconductor includes a base body including boron, a first nitride region including Alx1Ga1-x1N (0.98<x1?1), and a second nitride region including Alx2Ga1-x2N (0?x2<1, x2<x1). A concentration of boron in the base body is not less than 1×1019 cm?3. The first nitride region is between the base body and the second nitride region. The first nitride region includes a first surface facing the base body and a second surface facing the second nitride region. A second concentration of boron in the second surface is not more than 1/8000 of a first concentration of boron in the first surface.
    Type: Application
    Filed: August 1, 2022
    Publication date: May 4, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hajime NAGO, Jumpei TAJIMA, Toshiki HIKOSAKA
  • Patent number: 11641670
    Abstract: According to one embodiment, a wireless communication device includes: a receiver that configured to receives a first frame; and a transmitter that configured to transmits a second frame including a first identifier and acknowledgement information on the first frame, the first identifier being extracted from a predetermined field of the first frame and being different from a source address of the first frame.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: May 2, 2023
    Assignee: TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Tomoko Adachi, Masahiro Sekiya, Takeshi Tomizawa, Daisuke Taki, Masaaki Ikuta, Tomoya Suzuki
  • Patent number: 11639961
    Abstract: A first circuit outputs a third signal having a first level during a period over which first and second signals have the same level, and having a second level during a period over which the first and second signals have different levels. A second circuit outputs a fifth signal having the first level during a period over which a fourth signal having the same level as the third signal has the same level as the first signal, and having the second level during a period over which the first and fourth signals have different levels. A third circuit outputs a sixth signal having a third level during a period over which the second and fifth signals have the same level, and having a fourth level during a period over which the second and fifth signals have different levels.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: May 2, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Kenji Suina
  • Patent number: 11640991
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, first, second, and third semiconductor regions, an insulating portion, a conductive portion, a gate electrode, and a second electrode. The first semiconductor region is provided on the first electrode and electrically connected to the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The insulating portion are arranged with a portion of the first semiconductor region, and the second and third semiconductor regions. The conductive portion is provided inside the insulating portion and arranged with the first semiconductor region. The gate electrode is provided inside the insulating portion and arranged with the second semiconductor region. The second electrode is provided on the third semiconductor region and electrically connected to the third semiconductor region.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: May 2, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroaki Katou, Yasuhiro Kawai, Atsuro Inada, Toshifumi Nishiguchi
  • Patent number: 11636876
    Abstract: According to one embodiment, a magnetic disk device includes a magnetic disk, a spindle motor, a magnetic head, a ramp load mechanism, a filter, and a control section. The control section rotates the spindle motor at a second rotating speed for a given period of time at startup of the device, and then loads the magnetic head from the ramp load mechanism to a prescribed position on the magnetic disk. The second rotating speed is higher than a first rotating speed at which the spindle motor is rotated at the magnetic head reads/writes data from/to the magnetic disk.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: April 25, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Koji Miyake, Takuya Ogawa, Wataru Tsukahara
  • Publication number: 20230123438
    Abstract: A semiconductor device includes first and second electrodes, a semiconductor part therebetween, and a control electrode between the semiconductor part and the first electrode. The semiconductor part includes first, third and fifth layers of a first conductivity type and second and fourth layers of a second conductivity type. The second layer is provided between the first layer and the first electrode. The third layer is provided between the second layer and the first electrode. The fourth layer and the fifth layer are selectively provided between the first layer and the second electrode. In a method for controlling the semiconductor device, first to third voltages are applied in order to the control electrode while a p-n junction between the first and second layers is biased in a forward direction. The second and third voltages are greater than the first voltage, and the third voltage is less than the second voltage.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Ryohei GEJO, Tatsunori SAKANO
  • Publication number: 20230121970
    Abstract: A semiconductor device includes a semiconductor part, a first electrode at a back surface of the semiconductor part; a second electrode at a front surface of the semiconductor part; third and fourth electrodes provided between the semiconductor part and the second electrode. The third and fourth electrodes are arranged in a first direction along the front surface of the semiconductor part. The third electrode is electrically insulated from the semiconductor part by a first insulating film. The third electrode is electrically insulated from the second electrode by a second insulating film. The fourth electrode is electrically insulated from the semiconductor part by a third insulating film. The fourth electrode is electrically isolated from the third electrode. the third and fourth electrodes extend into the semiconductor part. The fourth electrode includes a material having a larger thermal conductivity than a thermal conductivity of a material of the third electrode.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Takeshi Suwa, Tomoko Matsudai, Yoko Iwakaji
  • Patent number: 11631423
    Abstract: According to one embodiment, a magnetic recording device includes a magnetic head and a controller. The magnetic head includes a first magnetic pole, a magnetic element including a first magnetic layer, and a coil. The controller is electrically connected to the magnetic element and the coil. The controller is configured to supply a recording current to the coil and supply an element current to the magnetic element. The recording current includes a first period of a first polarity, a second period of a second polarity, a third period that shifts from the first to second period, and a fourth period that shifts from the second to first period. The element current includes DC and AC components. The AC component in the first period is the same as the AC component in the second period, the AC component in the third period, and the AC component in the fourth period.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: April 18, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yuji Nakagawa, Naoyuki Narita, Masayuki Takagishi, Tazumi Nagasawa, Tomoyuki Maeda
  • Patent number: 11631706
    Abstract: According to one embodiment, a light receiving device, includes pixel regions, each comprising a photoelectric transducer. Each photoelectric transducer is connected to a quenching resistor. A deep trench isolation structure surrounds and separates each pixel region. A plurality of shallow trench isolation portions is in the light receiving device. Each shallow trench isolation portion is below a quenching resistor and on a portion the deep trench isolation structure.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: April 18, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Koichi Kokubun
  • Patent number: 11632104
    Abstract: According to one embodiment, a semiconductor device includes a first switch element including a first end to which a first voltage is applied, and a second end and a gate electrically coupled to a first node, a second switch element including a first end to which a second voltage is applied, and a second end and a gate electrically coupled to the first node, a third switch element including a first end to which the second voltage is applied, a second end electrically coupled to a second node, and a gate coupled to the first node, a fourth switch element including a gate coupled to the second node, and a first terminal electrically coupled to a first end of the fourth switch element and outputting a signal based on a voltage of the second node.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: April 18, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Tsuneyuki Hayashi
  • Patent number: 11626132
    Abstract: According to one embodiment, a magnetic disk device includes a magnetic disk, a magnetic head, a control unit, and a setting unit. The magnetic head includes a write element which writes data to the magnetic disk and heater elements which adjust a levitation amount relative to the magnetic disk. The setting unit sets a heater value to be set on the basis of a measurement result of measuring the recording quality of the data written to the magnetic disk. The control unit controls electric power to be supplied to the heater elements on the basis of the heater value to be set to the setting unit.
    Type: Grant
    Filed: December 20, 2021
    Date of Patent: April 11, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Gaku Koizumi
  • Patent number: 11626131
    Abstract: According to one embodiment, a magnetic head includes a protective layer. When an element unit is a magnetic recording element unit, the protective layer includes a first region on a magnetic recording element protrusion and a second region on a magnetic recording element shield, the first region and the second region being flush with each other, or the first region being recessed more than the second region. When the element unit is a magnetic reading element unit, the protective layer includes a third region on a magnetic reading element protrusion and a fourth region on a magnetic reading element shield, the third region and the fourth region being flush with each other, or the third region being recessed more than the fourth region.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: April 11, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Kan Takahashi
  • Patent number: 11626130
    Abstract: According to one embodiment, a magnetic head includes a first magnetic pole, a second magnetic pole, and a stacked body provided between the first and second magnetic poles. The stacked body includes a first magnetic layer, a second magnetic layer provided between the first magnetic pole and the first magnetic layer, a third magnetic layer provided between the first magnetic pole and the second magnetic layer, a first nonmagnetic layer provided between the first magnetic layer and the second magnetic pole, a second nonmagnetic layer provided between the second and first magnetic layers, and a third nonmagnetic layer provided between the third and second magnetic layers. The third magnetic layer includes first and second elements. The first and second magnetic layers do not include the second element. Or concentrations of the second element in the first and second magnetic layers are less than in the third magnetic layer.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: April 11, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Naoyuki Narita, Masayuki Takagishi, Hitoshi Iwasaki, Tomoyuki Maeda
  • Patent number: 11626514
    Abstract: A semiconductor device includes: a first semiconductor layer of first conductivity type; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a first electrode provided in a first trench, the first trench reaching the second semiconductor layer from above the first semiconductor region, the first electrode facing the first semiconductor region via a first insulating film; a second electrode provided in a second trench, the second trench reaching the second semiconductor layer from above the first semiconductor region, the second electrode facing the first semiconductor region via a second insulating film; a third electrode including a first electrode portion, a second electrode portion provided on the first electrode portion and a third electrode portion provided on
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: April 11, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroyuki Kishimoto, Hiroaki Katou
  • Patent number: 11621556
    Abstract: A protective circuit includes a first line, a second line, and a signal line. A first and second diode are connected in series between the first and second lines. A resistor and a capacitor are connected between the first and second lines. A first inverter, a second inverter, a third inverter are connected in series between a node between the resistor and capacitor and a gate of a first transistor. A third diode is connected between the first and second lines. The first transistor is connected between the first and second lines. A second transistor is connected between the first line and a protected circuit. A gate of the second transistor is connected to the output of the first inverter. A third transistor is connected between the second line and the protected circuit. A gate of the third transistor is connected to output of the second inverter.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: April 4, 2023
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Munenori Sakai, Shinji Fujii
  • Patent number: 11619720
    Abstract: According to an embodiment, a distance measuring device is a signal processing device that performs processing on time-series luminance signals of each of frames acquired on the basis of reflected lights of laser lights irradiated in order in a plurality of predetermined directions for each of the frames. The distance measuring device includes a storage circuit and a selection circuit. The storage circuit stores information concerning a distance value obtained on the basis of a time-series luminance signal of a preceding frame. The selection circuit selects a peak based on the distance value as a candidate of the distance value out of peaks in the time-series luminance signal in a present frame.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: April 4, 2023
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi Kubota, Nobu Matsumoto