Abstract: An insulating device includes a first element, a second element, a first lead, a second lead, and a resin member. The second element is electrically connected to the first element. The first element is mounted on the first lead. The second lead includes a first surface and a second surface, the second surface being at a side opposite to the first surface. The second element is mounted to the first surface. the second lead is arranged to overlap the first element in a direction crossing the second surface of the second lead. The resin member seals the first element, the second element, the first lead, and the second lead.

Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer; a first insulating film extending downward from an upper surface of the first semiconductor layer, the first insulating film being columnar; a second electrode located in the first insulating film, the second electrode extending in a vertical direction, the second electrode being columnar; a second semiconductor layer partially provided in an upper layer portion of the first semiconductor layer, the second semiconductor layer being next to the first insulating film with the first semiconductor layer interposed; a third semiconductor layer partially provided in an upper layer portion of the second semiconductor layer; and a third electrode located higher than the upper surface of the first semiconductor layer, the third electrode overlapping a portion of the first insulating film, a portion of the first semiconductor layer, and a portion of the second semiconductor layer when viewed from above.

Abstract: According to one embodiment, a semiconductor device c includes: a package substrate including a base including a mount portion, and terminals; a semiconductor chip including a first pad to which a ground voltage is supplied, a second pad electrically connected to a first terminal among the terminals, and a semiconductor circuit connected to the first and second pads, the semiconductor chip being provided above the mount portion; and a first capacitor chip including a first capacitor unit provided in a silicon substrate, a first node supplied with the ground voltage, and a second node electrically connected to the second pad, the first capacitor chip being provided above the mount portion.

Abstract: A semiconductor device includes: a die pad having a top surface; a semiconductor chip provided on the top surface; a first solder provided between the top surface and the semiconductor chip, the first solder bonding the top surface and the semiconductor chip; a first metal film provided on the semiconductor chip; a first insulating film provided on the first metal film and having a first opening; a connector having a first end and a second end, the first end being provided on the first metal film in the first opening; a second metal film provided in the first opening, the second metal film having a plurality of second openings provided so as to surround a portion of the first metal film in contact with the first end, and the second metal film being provided between the first end of the connector and the portion of the first metal film; a plurality of second insulating films provided in direct contact with the first metal film in each of the second openings; and a second solder provided between the second meta

Abstract: According to one embodiment, a magnetic disk device includes a magnetic disk, a magnetic head, an electric power supply section, a control section, and an address storage section. The control section reads data from the magnetic disk by means of the read head on the basis of the address stored in the address storage section at predetermined timing, and writes the read data to the magnetic disk by means of the write head without suppressing the magnetic field range.

Abstract: An optical coupling device includes a light receiving element including a first output terminal and a second output terminal, a light emitting element provided on the light receiving element, a first switching element, a first electrode plate, and a sealing member. The first switching element includes a first main terminal connected to the first output terminal, a first control terminal connected to the second output terminal, and a second main terminal. An upper surface of the first electrode plate is connected to the second main terminal. The sealing member covers the light receiving element, the light emitting element, and the first switching element. A lower surface of the first electrode plate is exposed on a lower surface of the sealing member. The lower surface of the first electrode plate and the lower surface of the sealing member form the same plane.

Abstract: According to one or more embodiments, a semiconductor device includes a mounting substrate and a semiconductor element on the mounting substrate. The mounting substrate has a first electrode pad and a second electrode pad. The semiconductor element has a supporting substrate, third and fourth electrode pads, first slits and second slits. The third and fourth electrode pads are provided on a first surface of the supporting substrate facing the mounting substrate. The first slits are provided both in the supporting substrate and in the third electrode pad. The second slits are provided both in the supporting substrate and in the fourth electrode pad. The semiconductor device further includes a first conductive bonding agent that connects the first electrode pad to the third electrode pad and a second conductive bonding agent that connects the second electrode pad to the fourth electrode pad.

Abstract: According to one embodiment, a method includes: supplying electrical energy to a first path by an inspection circuit with a short circuit between two first terminals through a first probe; and detecting an electrical characteristic on the first path by the inspection circuit. The two first terminals are included in a plurality of second terminals included in a flexible printed circuit board. The flexible printed circuit board includes: an electronic component including the inspection circuit and a plurality of third terminals; the plurality of second terminals; and a plurality of first wired lines connecting the plurality of second terminals and the plurality of third terminals. The first path is formed by: the two first terminals; two second wired lines connected to the two first terminals among the plurality of first wired lines; and two fourth terminals connected to the two second wired lines among the plurality of third terminals.

Abstract: A current detection device of an embodiment includes a conductor, a first magnetic field detector, a second magnetic field detector, and a conductive film. The conductor includes a first region, a second region, and a third region connecting an edge of the first region and an edge of the second region. The first magnetic field detector is disposed between the first and second regions. The second magnetic field detector is disposed opposite to the first magnetic field detector with respect to the third region. The conductive film is bonded to a conductor layer including a slit having a width larger than each of widths of magneto-sensitive parts of the first and second magnetic field detectors and covers the slit, the conductor layer being provided between the conductor and each of the first and second magnetic field detectors.

Abstract: A first chip includes a first surface, a second surface, a first semiconductor layer including a nitride semiconductor layer, a first electrode pad located at the first surface, a second electrode pad located at the first surface, a first gate pad located at the first surface, and a third electrode pad located at the first surface. A second chip is located on the first surface of the first chip. The second chip includes a third surface facing the first surface of the first chip, a fourth surface, a second semiconductor layer including a channel of a second conductivity type, a fourth electrode pad located at the fourth surface, a fifth electrode pad located at the third surface and bonded to the second electrode pad of the first chip, and a second gate pad located at the third surface and bonded to the third electrode pad of the first chip.

Abstract: A semiconductor device includes a first terminal, a second terminal, a first chip, and a resistance part. The first chip includes a substrate electrically connected to the second terminal, a nitride semiconductor layer located on the substrate, a first drain electrode located on the nitride semiconductor layer and electrically connected to the first terminal, a first source electrode located on the nitride semiconductor layer and electrically connected to the second terminal, and a substrate capacitance between the first drain electrode and the substrate. The resistance part is connected in series in a path including the substrate capacitance between the first drain electrode and the second terminal.

Abstract: A simulation method is a simulation method of a semiconductor device. The semiconductor device includes a first electrode, a second electrode, a semiconductor part located between the first electrode and the second electrode, an insulating member located inside the semiconductor part, a third electrode located inside the insulating member, and a fourth electrode located between the first electrode and the third electrode and located inside the insulating member. The method includes causing a value of a first resistance to change according to a value of a first voltage between the first electrode and the second electrode. The first resistance is connected between the second electrode and the fourth electrode.

Abstract: A semiconductor package includes a PDA chip, a MOS chip, and a wiring plate including a first principal surface and a second principal surface, the first principal surface being provided with a first rigid plate that is non-conductive and a second rigid plate that is conductive, the PDA chip being fixed to the first rigid plate by using a non-conductive bonding agent, a lower surface terminal of the MOS chip being soldered to the second rigid plate, the second principal surface being provided with an input terminal and an output terminal, the input terminal being electrically connected to the PDA chip, the output terminal being electrically connected to the second rigid plate.

Abstract: A semiconductor device includes a semiconductor chip and a metal plate. The semiconductor chip has first and second surfaces, four side surface, four corners, four sides. The four side surfaces connect the first surface and the second surface. Two of the four side surfaces contact each other at one of the four corners. The four side surfaces contact the second surface at the four sides. The first and second electrodes are provided at the first front side. The metal plate is connected to the second surface side of the semiconductor chip. The metal plate includes third and fourth surfaces, and a through-hole or a notch. The third surface is connected to the second surface of the semiconductor chip. The fourth surface is provided at a side opposite to the third surface. The through-hole or the notch extends through the metal plate from the fourth surface to the third surface.

Abstract: According to an embodiment, provided is a semiconductor device includes an insulating substrate; a first main terminal; a second main terminal; an output terminal; a first metal layer connected to the first main terminal; a second metal layer connected to the second main terminal; a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal; a first semiconductor chip and a second semiconductor chip provided on the first metal layer; and a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer. The second metal layer includes a first slit. Alternatively, the third metal layer includes a second slit.

Abstract: An isolator includes a lower electrode, a first insulating layer, a second insulating layer, an upper electrode, and a low permittivity portion. The first insulating layer is provided on the lower electrode, and includes a protruding portion in an upper portion of the first insulating layer. The second insulating layer is provided on the protruding portion, extends sideways from a region directly above the protruding portion, and has a specific permittivity higher than a specific permittivity of the first insulating layer. The upper electrode is in contact with an upper surface of the second insulating layer. The low permittivity portion is in contact with a side surface of the protruding portion and a lower surface of the second insulating layer. The low permittivity portion has a specific permittivity lower than the specific permittivity of the first insulating layer.

Abstract: Provided is a current detection device including a first stacked board; a second stacked board provided on a first region on the first stacked board; a third stacked board provided on a second region on the first stacked board; a magnetic measurement element provided in a third region on the first stacked board, the magnetic element provided between the first region and the second region; and a first coil provided on the magnetic measurement element or below the magnetic measurement element.

Abstract: A processor performance measurement apparatus according to an embodiment includes a processor, in which the processor detects that a memory access occurs, the memory access being required to execute processing units or execute execution units by a processor to be measured, performs first estimation for estimating switching of the processing units or the execution units and second estimation for estimating which of the one or more processing units the processing unit being executed is or to which of the one or more processing units the execution unit being executed corresponds based on an address of an access destination of the memory access, measures respective performances in the processing units or the execution units based on an estimation result of the first estimation, and aggregates respective measurement results of the performances for each of the processing units based on an estimation result of the second estimation.

Abstract: According to one embodiment, a head actuator includes a first suspension assembly including a first support plate, a first wiring member with first wiring lines, and a first head, and a second suspension assembly including a second support plate, a second wiring member with second wiring lines, and a second head. The first wiring lines include at least four first read lines and at least four first write lines. The second wiring lines include at least four second read lines and at least four second write lines. At least two of the first read lines and at least two of the first write lines are arranged at a position offset to the second read lines and the second write lines in a width direction of the wiring member.

Abstract: A rectangular-wave-signal generating circuit according to an embodiment comprises: a sawtooth-wave output circuit; a first detector; a second detector; and a first PWM-signal output circuit. The sawtooth-wave output circuit is configured to generate and output a sawtooth-wave signal synchronized with a clock signal. The first detector is configured to detect a first timing at which a potential of the sawtooth-wave signal exceeds a bottom potential. The second detector is configured to detect a second timing at which a potential of the sawtooth-wave signal exceeds a potential of a first pulse-width instruction voltage signal. The first PWM-signal output circuit is configured to generate a first PWM signal based on a time difference between the first timing and the second timing.