Abstract: A circuit is provided that solves the problem of implementing a fully balanced (differential) transimpedance amplifier with low-noise and wide bandwidth. This is accomplished by direct coupling the feedback resistors from the outputs of the amplifier to the inputs without the use of a blocking capacitor. The low frequency response is thereby improved and the problems created by a DC bias resistor that degrades the noise performance and, in some case, restricts the dynamic range (caused by pulse width distortion for large signals) are eliminated. The amplifier achieves higher voltage gain than prior designs and also results in lower noise and wider bandwidth. The differential nature of the amplifier provides good power supply rejection. While the preferred embodiment is particularly well-suited to GaAs MESFET technology, the invention can also be applied to silicon bipolar and MOS technology.

Abstract: A circuit is described herein which effectively multiplies the value of a capacitor. The circuit draws current from an input node, where this current being drawn is related to the gain of an amplifier and the value of a capacitor, thus effectively amplifying the capacitance value of a capacitor as seen at the input node.

Abstract: A method of forming substrate vias in a GaAs wafer begins with a GaAs wafer in which all top side processing steps are complete. The top surface of the GaAs wafer includes top surface via contacts, which are in electrical contact with the bottom surface ground plane once the ground vias are complete. A protective layer is formed on the top surface of the wafer to protect the finished integrated circuitry. A portion of the substrate is removed from the bottom surface to achieve a thin layer of substrate material. The bottom surface of the thinned substrate is metalized with a first metal layer. Laser via holes are drilled into the thinned substrate from the bottom surface of the wafer to within a few microns from the top surface metal via contacts. The laser holes are drilled by emitting a controlled number of single pulses over the selected via location.

Abstract: An integrating phase detector includes a phase comparator and an integrating load impedance. The phase comparator is a voltage-input, current-output logic gate such as a OR/NOR gate, or a XOR/XNOR gate having first and second inputs for comparing the phase of first and second input signals. The current output of the logic gate provides an output current pulse proportional to the phase difference between the first and second input signals. The integrating load such as a passive resistor-capacitor network is coupled to the current output of the phase detector for directly integrating the current pulse and providing a DC voltage proportional to the phase difference between the first and second input signals. The minimum pulse width of the output current pulse is substantially limited only by the fT of the devices used in the logic gate.

Abstract: A current mirror compensation circuit is disclosed herein which automatically adjusts the operating conditions of a current mirror so as to compensate for the voltage dependent current characteristics of a current load which a current mirror output is intended to match. In one embodiment, this compensation circuit compares a voltage level at the output of a current source with a voltage level at a corresponding node in the current programming portion of a current mirror. If a difference in these voltages is detected, the compensation circuit adjusts the current flow through the current programming portion of the current mirror to be equal to the output current through the current source. Therefore, since the current mirror output portion mirrors the current through the programming position, the currents through the output portion will match the current through the current source.

Abstract: A circuit is which, when used in a voltage controlled oscillator (VCO) circuit, detects a frequency on the output of the VCO and, if this output frequency is above a certain value, the circuit forces the output frequency of the VCO to decrease until it is below the certain value. This acts to keep the output frequency of the VCO below a selected frequency which can be accurately processed by the feedback circuits driven by the VCO. Once the output frequency of the VCO is below the certain value, the circuit stops forcing the output frequency to decrease, and the circuit becomes transparent. At this point, the conventional feedback circuitry driving the VCO takes over the adjustment of the VCO output frequency.

Abstract: An apparatus and method for improving the bit error rate of multiplexed signals in a multiplexer system includes independently controlling two types of timing errors. The first type of timing error is related to the timing of transitions between alternating portions of the multiplexed output signal. The second type of timing error is related to the amplitude of the crossing points of the multiplexed signal portions. Varying the duty cycle of the clock signal to the multiplexer controls the transition between the alternating portions of the multiplexed output signal, and adding a voltage offset between single-ended components of the multiplexed output signal controls the amplitude of the crossing points between the one/zero and zero/one transitions of the multiplexed outut signal. The two types of timing errors are controlled with two separate control voltage ports that are independently and continuously variable in order to achieve the optimum bit error rate.

Abstract: A tristate output driver circuit (30, 40, 50) includes first (Q7) and second (Q8) switches for selectively connecting a logic high voltage source (VH) or a logic low voltage source (VL) to an output terminal (12) in a first, connected mode. Control nodes (14, 16) on the first and second switches (Q7, Q8) are energized in a precise, symmetrical manner to prevent multiple slopes in the output waveform by a precision input stage (31) that includes cascode outputs (Q17, Q18), cascode current sources (Q19-Q20, Q21-Q22) and bootstrapped current sources (32, 34). In a second, tristate mode, the output terminal (12) is electrically isolated from the logic high (VH) and logic low voltage sources (VL). In the tristate mode, the off-switch remains off and the on-switch is turned off by the precision input stage (31) to minimize glitches in the output waveform.

Abstract: A method of fabricating an integrated circuit comprises providing a heavily compensated substrate having a source region, a drain region and a third region, each of a first conductivity type, and introducing dopant of a second conductivity type into the substrate to surround the third region.

Abstract: In a pipelined direct digital synthesis system (FIG. 3), new increment data (124) and/or phase modulation data (122) are input delay equalized by providing the data to a series of switch blocks (132), each switch block corresponding to a stage of the accumulator (124). Each switch block includes a multiplexer (132) for selecting among the new increment data, phase modulation data, and previously stored increment data, and includes a flip-flop circuit (134) for storing the selected increment data. A shift register (140) provides select signals (146) to each of the multiplexers. In operation, as a single bit propagates through the shift register, the select signals sequentially control the multiplexers to sequentially interleave blocks of selected increment data into respective accumulator stages in ascending order of binary significance. The invention thereby substantially reduces the input delay equalization circuitry necessary for coherent operation.

Abstract: A class AB amplifier comprises a pull-up structure of an E-FET and D-FET connected in parallel and a pull-down structure of an E-FET and D-FET connected in parallel. Use of the E-FETs allows a high peak current to be achieved without increasing the quiescent current to an undesirable level. The pull-up structure and the pull-down structure are driven by currents that are out-of-phase, and accordingly linear push-pull operation is provided.

Abstract: A compensation method and apparatus for enhancing single-ended to differential conversion includes a compensation network that is coupled between the single-ended voltage input and the bias terminal of a differential stage. The compensation network has an impedance substantially equal to the impedance presented by the bias circuit used to bias the differential stage. Accordingly, the compensation network provides a current that substantially cancels the signal tail current supplied to the bias terminal of the differential stage, resulting in a balanced differential output. The compensation network may be AC coupled from the single-ended voltage input to the bias terminal in order to preserve the original DC operating condition. The compensation network may be chosen to provide more cancelling current at higher operating frequencies. Additionally, the compensation network can be configured to match a bias circuit built from resistors, transistors, current mirrors, or the like.

Abstract: A high-gain solid-state amplifier (20) includes an amplification stage including a transistor (Q.sub.1) having a current-dependent transconductance value. The transistor is operatively connected to a load resistor (R.sub.L1) through which a load current (I.sub.1) flows. The value of the load resistor together with the transconductance value affects the voltage gain of the amplifier. A resistor (R.sub.2) provides a supplemental bias current (I.sub.2) to a current summing node (A). The current summing node sums the load current and the supplemental bias current and provides the transistor with a total current (I.sub.d) that affects the transconductance value. The value of the supplemental bias current is chosen to supplement the load current to provide a predetermined total current so that the voltage gain may be adjusted by adjusting the load resistor without changing the transconductance value.

Abstract: A transimpedance amplifier comprises a transconductance amplifier having a nonlinear resistive feedback element. The feedback element includes a pair of resistors and a pair of diodes, one of which conducts (depending upon the voltage polarity) only when the voltage across the diode exceeds the diode on-voltage. This includes additional resistance in the feedback element thereby changing the amplifier gain. The largest value of the resistive feedback element is substantially equal to or less than the output resistance of the transconductance amplifier. The feedback element is both symmetrical and nonlinear. A shunt amplifier is driven by circuit which produces a control signal that varies with a signal current. Increasing signal current increases the DC current shunted from the amplifier input thus decreasing pulse edge distortion and increasing dynamic range. A capacitor AC couples the current input to the amplifier.

Abstract: A high-gain, low noise solid-state multiple stage amplifier (12) includes a phase-inverting input stage (20) and a phase non-inverting output stage (30). The input stage includes a first transistor (Q.sub.1) having a current-dependent transconductance value. The first transistor is operatively connected to a load resistor (R.sub.L1) through which a load current (I.sub.1) flows. An amplified phase-inverted version of a time-varying signal applied to the input (V.sub.i) is developed across the load resistor. The value of the load resistor together with the transconductance value affects the voltage gain of the input stage. A resistor (R.sub.2) provides a supplemental bias current (I.sub.2) to a current summing node (A). The current summing node sums the load current and the supplemental bias current and provides the first transistor with a total current (I.sub.d) that affects the transconductance value.

Abstract: An electrical circuit (30) corrects for the presence of noise current and current drift in the currents developed by each current source transistor Q.sub.0, Q.sub.1, Q.sub.2, Q.sub.3, . . . Q.sub.n in a current source array. The electrical circuit corrects for the presence of noise current and current drift by simultaneously inducing in each current source correction currents whose values sum to cancel the current drift and noise. A noise suppression circuit includes an amplifier having an open loop gain, A.sub.v, which is configured to adjust the magnitudes of the multiple currents in response to the introduction of a noise current, i.sub..delta., in any one of the currents. The adjustment substantially cancels i.sub..delta. and thereby substantially reduces the presence of i.sub..delta. in the output current. The presence of i.sub..delta. in the output signal is substantially equal to i.sub..delta. /(1+A.sub.v).

Abstract: An optical receiver circuit for an incoming optical signal having a variable power level includes an optical detector for receiving the optical signal and generating a current therefrom which varies with the optical signal power level. The current so generated is applied to a transimpedance amplifier. An automatic gain control (AGC) drive circuit is connected around the amplifier thereby increasing its dynamic range. The AGC drive circuit drives a FET which has one side thereof connected to the transimpedance amplifier for shunting current from the input thereof. A negative feedback circuit comprising an amplifier is connected across the FET, which comprises the resistive feedback element, thus reducing the FET resistance by a factor of 1+T, where T is the feedback circuit loop gain.

Abstract: A high-impedance FET circuit in which the anode of a diode is electrically connected to the first side of the FET and the diode's cathode is connected to the FET gate. The diode biases the FET to reduce second side current when the second side is at a positive potential relative to the diode cathode. Such circuits placed back-to-back accommodate signals of both polarities and are used as a high impedance element in a low-pass filter implemented in an integrated circuit. An equivalent symmetrical circuit implemented with two enhancement FETs is also disclosed.

Abstract: A method and apparatus for modulating or demodulating a radio frequency (RF) signal which incorporates a pair of quadrature couplers. In demodulating an RF signal, an LO signal and the RF signal are each phase shifted -90 degrees by the couplers. The RF and LO signals are mixed as are the phase-shifted RF and LO signals. Each mixed signal is low-pass filtered and the filtered signals are added thereby producing an intermediate frequency signal.

Abstract: A binarily weighted FET attenuator implemented in integrated form. The resistance of the vertical branches to the horizontal branches is at a ratio of 2:1. Each vertical branch includes a FET switch for switching between ground and a summing amplifier and each horizontal branch includes a FET permanently biased to conduct. Thus, variations in the value of r.sub.on, the resistance of each FET when conducting, due to fabrication process and temperature are compensated for due to the presence of FETs in both the vertical and horizontal legs of the attenuator.