Abstract: A DAC includes a simple width-scaled weighted array (104) of N number of current sources and a weighted cascode current divider (108) comprised of m number of current sources. The simple width-scaled weighted array conducts N first scaled currents (I.sub.0 -I.sub.3), the array including N first transistors (116a-116d) connected to different ones of N second transistors (112a-112d), one of the N second transistors (112d) having a gate width w. The weighted cascode current divider includes M current sources, the current divider including M third transistors (120a-120d) that conduct M second scaled currents (I.sub.4 -I.sub.7) which are summed at a node (134). The node is connected to a master current transistor (138) that conducts a current I.sub.S and has a gate width w.

Abstract: An analog to digital converter with second order error correction provides a more accurate digital output code for a high frequency input analog signal. A slope of the input signal is determined from the digital output code of a quantizer, and the slope is used to provide a correction value that is a function of the slope. The correction value may also be a function of a level range of the quantizer. The correction value is added to the digital output code to produce a corrected digital output code.

Abstract: A variable FET attenuator uses feedback in a control loop to correct the attenuator automatically for input/output return loss as the attenuator is varied with a control signal input. Both the series and shunt variable FETs are set to the proper conductance to maintain a proper input match with a desired attenuation value. A second, reference attenuator circuit provides feedback control of the primary attenuator circuit through an operational amplifier. The reference circuit is designed to be electrically equivalent to the attenuator circuit in terms of characteristic impedance. The control nodes, and attenuation control signal input and an output from the operational amplifier, are paralleled so that both the reference and primary attenuator circuits behave identically, without having to RF decouple the feedback loop from the attenuator circuit. Preferably, identical bridged-T variable attenuators are used for both the attenuator circuit and the reference circuit.

Abstract: A differential amplifier includes a pair of input transistors for directing portions of a load current from a current source through a pair of load transistors in response to a differential input signal. A common mode output voltage of the differential amplifier is detected and applied to control terminals of a pair of feedback transistors. The feedback transistors couple the load transistors to a reference voltage and act therewith to provide control currents through the load transistors concurrent with the load currents. The control currents provide feedback that maintains the common mode output voltage at a constant threshold level.

Abstract: A wafer probe comprises a support member having an end region which is shaped to permit the end region to be brought into close proximity with a component under test. An amplifier is mounted on the support member at its end region. A conductive probe element is attached to the amplifier and is electrically connected to the amplifier's input terminal. A transmission line is connected to the amplifier's output terminal for transmitting signals from the amplifier to a measurement instrument.

Abstract: An output stage for producing a high accuracy differential output signal includes a first differential amplifier providing a pair of single-ended first signals of magnitudes that swing in opposite directions between first and second levels following a change in level of an input signal. A sum of magnitudes of the first signals is controlled by an input control current. The first signals provide input to a second differential amplifier supplying a pair of single-ended second signals swinging in opposite directions between third and fourth levels when the first signals change levels, the second signals forming the differential output signal of the output stage. An indicating signal, provided by the second differential amplifier, supplies a measure of a sum of magnitudes of the second signals. A third differential amplifier produces the control current of magnitude determined by a magnitude difference between the indicating signal and a constant reference signal.

Abstract: A tristate output circuit includes a pair of transistors having sources connected to a switchable current source and drains separately coupled to a voltage source through separate resistors and switching transistors. When the current source and switching transistors are on, the circuit operates in a back termination mode wherein it amplifies a differential input signal applied across the gates of the transistor pair to produce a differential output signal across their drains for transmission on a transmission line. The load resistors are sized to match the characteristic impedance of a transmission line so as to properly terminate the transmission line. In an open drain mode, the switching transistors are off, uncoupling the drains of the transistor pair from the voltage source so as to increase output impedance. In a tristate mode, the current source and switching transistors are turned off, thereby turning off the transistor pair and rendering the output impedance of the circuit substantially infinite.

Abstract: A method for removably securing the leads of a semiconductor package to the conductive pathways on a circuit board is disclosed. Specifically, a retaining member is provided which includes a plurality of bores each sized to receive a pressure pin. Each pin communicates with a biasing system, enabling the resilient movement of each pin independently of the other pins. The retaining member and pins are positioned above the semiconductor package on the circuit board, and subsequently urged downward so that each pin contacts one of the leads on the package. As a result, the proper pressure is applied to each pin so that it effectively communicates with its designated conductive pathway on the circuit board.

Abstract: A method of electrolytic deposition of metal is used to decrease the minimum size pattern that can be obtained using photolithography. In the manufacture of integrated circuits, a layer of metal and then photoresist is deposited on the dielectric layer of the substrate prior to masking to define the gate apertures. After masking and etching through to the dielectric, metal is electrodeposited on the metal edges that abut the gate aperture, thus decreasing the aperture size. After that decreased gate dimension is etched into the dielectric to define the gate lengths of the semiconductor devices, the wafer is stripped and the subsequent manufacture proceeds in the conventional manner.

Abstract: In an integrated circuit, a reference voltage proportional to the pinchoff voltage of a field effect transistor is created by providing a current source, including a first depletion-mode FET, and a second depletion mode FET having a source connected to the drain of the first FET at an output node. The first and second FETs have their source and drain, respectively, connected to the first and second supply voltages, respectively, so that in operation, substantially equal currents flow through the two transistors. The FETs are biased to operate in saturation. Regarding the first FET, this current is equal to I.sub.DSS (defined as I.sub.D when V.sub.GS =0) of the first FET (I.sub.DSS1) and is not greater than, and usually less than, I.sub.DSS of the second FET (I.sub.DSS2). The dimensions of the FETs are proportioned such that the gate-source voltage across the second FET substantially equals a constant times the pinchoff voltage.

Abstract: The source and drain of a first depletion-mode MESFET (DFET) define the controlled current path of a switch, the switch being open or closed depending on whether the gate-to-source voltage (V.sub.gs) for the first DFET is greater or less than the pinch-off voltage (V.sub.p) for the first DFET. The first DFET has its gate connected to a first circuit node. A second DFET, connected as a source follower, has its gate connected to the source of the first DFET. A first diode has its anode connected to the first circuit node and its cathode connected to a second circuit node. A second diode has its cathode connected to the second circuit node and its a node connected to the source of the second DFET. At least one additional diode is connected anti-parallel to the first diode between the first and second nodes.

Abstract: In a GaAs integrated circuit, a voltage reference generator includes a pair of Schottky diodes and a first, current-source connected, depletion-mode MESFET coupled in series to conduct current from a ground node to a voltage supply node. The current-source connected FET causes a constant current to flow from the ground node through the diodes, producing a constant voltage drop which generates a constant reference voltage at a reference node between the diodes and FET. A second pair of Schottky diodes is connected in series between the source of the FET and the voltage supply node, in a loop coupling the source to the gate of the FET, to provide a voltage difference Vgs across the FET proportional to voltage drop across the second pair of diodes. This voltage difference varies with fabrication process and temperature variations and causes the first FET to modify the amount of current flow to compensate so as to maintain a constant voltage drop across the first pair of diodes.

Abstract: An integrated circuit gate process and structure are disclosed which provide a self-aligned, recessed gate enhancement-mode GaAsFET. The process includes making self-aligned implants prior to gate metallization, with an intermediate step of applying patches of plasma- and chemical-etch resistant dielectric, such as zirconium oxide (ZrO), over the self-aligned implants to fixedly define gate length. The self-aligned gate process includes stair-stepping three successive implants, in respect to both depth and concentration, to provide a dopant concentration gradient inclined depthwise away from each side of the gate. The self-aligned, recessed gate GaAsFET exhibits improved source-gate resistance without degradation of gate-drain capacitance, increased gain and drain-source current, and reduced knee-voltage. Gate length is minimized to the limits of photolithography without degrading input resistance.

Abstract: A self-aligned gate GaAsFET fabrication process and structure are disclosed in which the gate metallization is offset to one side of the channel aligned with the source-side implant. The arrangement is advantageously provided by a photolithographic fabrication process in which a pair of self-aligned implants are made, before gate metallization. As an intermediate step, a first etch-resistant ZrO patch is deposited over at least one of the self-aligned implants aligned therewith. Then, a second such patch is deposited which overlaps the other self-aligned implant and extend a distance over the channel between the two implants. The first and second patches are thereby spaced closer together (e.g., 0.5 .mu.m) than the implants (e.g., 1.0 .mu.m). The patches fix the gate length at less than implant spacing and offset the gate metallization along the source-side self-aligned implant, away from the drain implant. The gate is preferably recessed.

Abstract: A gallium arsenide differential amplifier is compensated against temperature and process induced variations so as to provide phase and amplitude matched differential output signals centered about an internal GaAs reference voltage. Compensation of the amplifier is effected by one or more current sources which are adjustably responsive to the dynamic common mode level of the output signals. The resultant amplifier provides a high common mode rejection ratio and facilitates implementation of otherwise impracticable differential GaAs circuit topologies.

Abstract: Field effect transistors are manufactured using a substrate of compound semiconductor material by defining two gate areas which have their longitudinal dimensions so oriented with respect to the crystal axes of the substrate that the substrate material is more readily etchable through one of the gate areas than through the other gate area. The semiconductor material is etched through both the gate areas simultaneously with the same etchant, whereby gate recesses of different respective depths are formed in the substrate. Metal is deposited into the recesses.