Abstract: An RF transmitter provides both GSM and EDGE capability by implementing collector voltage control over the power transistor(s) in a power amplifier. During EDGE mode, linear base-biasing a power amplifier (PA) allows collector control to provide either saturated mode PA operation (during ramp up/ramp down) or linear mode PA operation (during data burst). Collector control can therefore be used to provide the accurate ramp up and ramp down profiles required for both GSM and EDGE burst output signals, and can also be used to set the level of the constant envelope data burst of a GSM burst output signal, while linear mode PA operation can provide the non-constant envelope EDGE data burst. A variable gain amplifier is used to adjust the input signal to the power amplifier such that the desired transmission level is achieved.

Abstract: A power amplifier comprises an input terminal, an output terminal and a first amplification stage coupled with the input and output terminals. The first amplification stage having a node and a resistive structure coupled with the node. The resistive structure includes a first resistive circuit coupled with the node; and an adaptation circuit coupled with the first resistive circuit such that when the first amplification stage is in a first mode, the resistive structure provides a first effective resistance and when the first amplification stage is in a second mode, the resistive structure provides a second effective resistance.

Abstract: A peak detector detects an amplifier output overvoltage condition if the amplifier drives a mismatched load impedance. In response to the detected overvoltage condition, a clamping transistor lowers a reference DC bias voltage supplied by a bias circuit to the amplifier. The lowered reference DC bias voltage lowers amplifier gain and output power, thus protecting the amplifier.

Abstract: A photodetector includes a high-indium-concentration (H-I-C) absorption layer having a Group III sublattice indium concentration greater than 53%. The H-I-C absorption layer improves responsivity without decreasing bandwidth. The photoconversion structure that includes the H-I-C absorption layer can be formed on any type of substrate through the use of a metamorphic buffer layer to provide a lattice constant gradient between the photoconversion structure and the substrate. The responsivity of the photodetector can be further improved by passing an incoming optical signal through the H-I-C absorption layer at least twice.

Abstract: A single port multi-resonator acoustic resonator device (200, 300, 400, 490) possesses an input impedance that exhibits precisely designed electrical resonances. The device contains at least three parts: a transducer/resonator (201, 301, 401. 491) used both to interface to an external electrical circuit and to transform electrical energy into mechanical (i.e. acoustic) vibrations (and vice versa), and also function as a resonator; a mechanical (i.e. acoustic) resonator (203, 303, 460, 480) and an acoustic coupler (202, 302, 404, 494) that controls the acoustic interaction between the transducer/resonator and the mechanical resonator.

Abstract: A circuit includes a transmission line transformer coupled between an input and output port. An inductor may be selectively coupled into the ground return path of the transmission line transformer to alter the impedance transformation provided between the input and output ports.

Abstract: A power amplifier having a first amplifier output stage and a parallel second amplifier output stage is provided. The first amplifier output stage is enabled (i.e., fully biased) during both high power and low power operating modes. The second amplifier output stage is disabled during the low power operating mode, and enabled during the high power operating mode. Because neither the first nor second amplifier output stage is operated in an extremely low quiescent current state, the linearity of the power amplifier is maintained for both high power and low power operating modes.

Abstract: A bias circuit includes a regulator circuit an d a current diverting circuit. The regulator circuit includes a load resistor, a first transistor, and feedback control circuitry for biasing the first transistor such that a nominal quiescent current flows through the first resistor and first transistor. A current diverting circuit is coupled in parallel with the first transistor. When the current diverting circuit is disabled, the nominal quiescent current continues to flow through the load resistor and first transistor. When the current diverting circuit is enabled, a diverted current flows through the current diverting circuit, such that the new quiescent current through the first transistor is equal to the nominal quiescent current minus the diverted current. The value of the diverted current is also controlled by the feedback control circuitry. The quiescent current through the first transistor is used as a reference for biasing another circuit.

Abstract: A multi-stage amplifier is coupled with a power detector. The multi-stage amplifier includes a plurality of amplifier stages in series, with a signal path extending through them. The power detector is coupled to an interior node of the amplifier along the signal path, and is operable to sample a first signal being transmitted on the signal path. The power detector outputs a second signal reflective of a power of the first signal. In one embodiment, the interior node is in a matching network of the amplifier disposed between a first amplifier stage and a final amplifier stage of the amplifier. The second signal may be used in a feedback network to adjust an amount of amplification of the first signal by the amplifier.

Abstract: A passivation layer for a heterojunction bipolar transistor (HBT) is formed from a relatively high bandgap material that is lattice-matched to the HBT components it passivates. By selecting the passivation layer to have a higher bandgap than the HBT components, minority carriers are contained within the HBT by the passivation layer. At the same time, the lattice matching of the passivation layer ensures a robust bond that prevents the subsequent formation of dangling bonds at the exterior surfaces of the base and collector (and/or other passivated surfaces), thereby minimizing surface leakage currents.

Abstract: A depletion mode (D-mode) field effect transistor (FET) is monolithically integrated with an enhancement mode (E-mode) FET in a multi-layer structure. The multi-layer structure includes a channel layer overlaid by a barrier layer overlaid by an ohmic contact layer. Source and drain contacts of the D-mode and E-mode FETs are coupled to the ohmic contact layer. A gate contact of the D-mode and E-mode FETs is coupled to the barrier layer. An amorphized region is provided beneath the E-mode gate contact within the barrier layer. The amorphized region forms a buried E-mode Schottky contact with the barrier layer. An alternative embodiment couples the gate contact of the D-mode transistor to a first layer that overlies the barrier layer, and provides a similar D-mode amorphized region within the first layer.

Abstract: A multi-stage amplifier is coupled with a power detector. The multi-stage amplifier includes a plurality of amplifier stages in series, with a signal path extending through them. The power detector is coupled to an interior node of the amplifier along the signal path, and is operable to sample a first signal being transmitted on the signal path. The power detector outputs a second signal reflective of a power of the first signal. In one embodiment, the interior node is in a matching network of the amplifier disposed between a first amplifier stage and a final amplifier stage of the amplifier. The second signal may be used in a feedback network to adjust an amount of amplification of the first signal by the amplifier.

Abstract: Decoder logic for an RF switch includes first and second enhancement mode transistors and a depletion mode transistor. Sources of the depletion mode transistor and the first enhancement mode transistor are coupled to a VDD supply. The drain and gate of the depletion mode transistor are coupled to the gate of the first enhancement mode transistor. The second enhancement mode transistor is coupled between ground and the drain of the depletion mode transistor. In active mode, the second enhancement mode transistor is turned off and the depletion mode transistor applies a high voltage to the gate of the first enhancement mode transistor, thereby turning on the first enhancement mode transistor to couple the RF switch the VDD supply. In inactive mode, the second enhancement mode transistor is turned on, thereby turning off the first enhancement mode transistor and providing a low current path between the VDD supply terminal and ground.

Abstract: A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying transistor. The sense current causes a sense voltage at the collector terminal of the sense transistor. This sense voltage is applied to one input of an error amplifier. The other error amplifier input receives a power control voltage. The error amplifier output is routed back to the base terminal of the amplifying transistor in a negative feedback loop, thereby keeping the power of the signal output by the amplifying transistor at a constant level. In some embodiments the error amplifier output is made independent of changes in the reference voltage. Multiple pairs of corresponding amplifying and sense transistors can be used.

Abstract: A power amplifier having a first amplifier output stage and a parallel second amplifier output stage is provided. The first amplifier output stage is enabled (i.e., fully biased) during both high power and low power operating modes. The second amplifier output stage is disabled during the low power operating mode, and enabled during the high power operating mode. Because neither the first nor second amplifier output stage is operated in an extremely low quiescent current state, the linearity of the power amplifier is maintained for both high power and low power operating modes.

Abstract: A power amplifier having a first amplifier output stage and a parallel second amplifier output stage is provided. The first amplifier output stage is enabled (i.e., fully biased) during both high power and low power operating modes. The second amplifier output stage is disabled during the low power operating mode, and enabled during the high power operating mode. Because neither the first nor second amplifier output stage is operated in an extremely low quiescent current state, the linearity of the power amplifier is maintained for both high power and low power operating modes.

Abstract: A transmission line element is formed in an integrated circuit chip. The transmission line element includes a plurality of parallel conductors, with each conductor including a plurality of electrically connected transmission lines. At least two of the transmission lines of each conductor are in different ones of plural metal layers of the integrated circuit chip. The metal layers are separated by at least one dielectric layer. Each transmission line in each conductor is edge-coupled to a transmission line of another of the conductors, and broadside-coupled to a transmission line of another of the conductors. The transmission line element can be used, for example, to fabricate various types of balanced and unbalanced transformers.

Abstract: A bias control circuit generates a bias control current that is proportional to temperature. The bias control current is drawn from a first node of a bias circuit. The first node of the bias circuit is also configured to receive a relatively large first current that is also proportional to temperature. A bias current is also drawn from the first node, wherein the bias current is equal to the difference between the relatively large first current and the bias control current. The temperature sensitivities of the bias control current and the relatively large first current are matched, such that the bias control current is relatively insensitive to changes in temperature.

Abstract: A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying transistor. The sense current causes a sense voltage at the collector terminal of the sense transistor. This sense voltage is applied to one input of an error amplifier. The other error amplifier input receives a power control voltage. The error amplifier output is routed back to the base terminal of the amplifying transistor in a negative feedback loop, thereby keeping the power of the signal output by the amplifying transistor at a constant level. In some embodiments the error amplifier output is made independent of changes in the reference voltage. Multiple pairs of corresponding amplifying and sense transistors can be used.

Abstract: A sense transistor is placed in a current path between a reference voltage source and ground. The base terminal of the sense transistor is coupled to the base terminal of an amplifying transistor. Thus, current in the sense transistor corresponds to signal power output by the amplifying transistor. The sense current causes a sense voltage at the collector terminal of the sense transistor. This sense voltage is applied to one input of an error amplifier. The other error amplifier input receives a power control voltage. The error amplifier output is routed back to the base terminal of the amplifying transistor in a negative feedback loop, thereby keeping the power of the signal output by the amplifying transistor at a constant level. In some embodiments the error amplifier output is made independent of changes in the reference voltage. Multiple pairs of corresponding amplifying and sense transistors can be used.