Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs). In embodiments, a body-bias circuit may derive a bias voltage based on a radio frequency signal applied to a switch field-effect transistor and apply the bias voltage to the body terminal of the switch field-effect transistor.

Abstract: Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed.

Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs). In embodiments, a resistive divider comprising a first resistor and a second resistor may be coupled with the FET at a position electrically between a gate terminal of the FET and a body terminal of the FET.

Abstract: Embodiments include but are not limited to apparatuses and systems including a buffer layer, a group III-V layer over the buffer layer, a source contact and a drain contact on the group III-V layer, and a regrown Schottky layer over the group III-V layer, and between the source and drain contacts. The embodiments further include methods for making the apparatuses and systems. Other embodiments may be described and claimed.

Abstract: Embodiments of circuits, apparatuses, and systems for a quadrature hybrid circuit are disclosed. The quadrature hybrid circuit may include a ladder structure, may act as a combiner or a divider, and may transform a source impedance to a load impedance.

Abstract: Embodiments provide a radio frequency (RF) power amplifier (PA) circuit having a high-power mode and a low-power mode. The RF PA circuit may include a high-power amplifier to provide an amplified RF signal on a first path, and a low-power amplifier to provide an amplified RF signal on a second path. The first path and second path may intersect at a junction node. A switch may be coupled between the low-power amplifier and the junction node to switch the circuit between the high-power mode and the low-power mode. A matching circuit may be coupled on the second path to match an output impedance of the low-power amplifier to a junction impedance of the junction node at a fundamental frequency of the RF signal, and to present an open circuit at a third harmonic of the RF signal. The matching circuit may facilitate high efficiency for the RF PA circuit.

Abstract: An apparatus and method is disclosed for providing an electrostatic discharge protection circuit for compound semiconductor devices and circuits. The electrostatic discharge protection circuit comprises a first terminal and a second terminal. The electrostatic discharge protection circuit further comprises a transistor shunt element that is operably coupled between the first terminal and the second terminal; the transistor shunt element is capable of providing a bi-directional discharge path between the first terminal and the second terminal. The electrostatic discharge protection circuit further comprises a shut-off element that is operably coupled with the second terminal; the shut-off element is capable of keeping the transistor shunt element turned-off.

Abstract: Embodiments include but are not limited to apparatuses and systems including a field-effect transistor switch. A field-effect transistor switch may include a first field plate coupled with a gate electrode, the first field plate disposed substantially equidistant from a source electrode and a drain electrode. The field-effect transistor switch may also include a second field plate proximately disposed to the first field plate and disposed substantially equidistant from the source electrode and the drain electrode. The first and second field plates may be configured to reduce an electric field between the source electrode and the gate electrode and between the drain electrode and the gate electrode.

Abstract: One embodiment of an electrostatic protection diode in an integrated circuit includes a base area having at least two bends therein.

Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N) and a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N). The IC device may further include a gate terminal and a gate dielectric layer disposed between the gate terminal and the barrier layer and/or between the gate terminal and the buffer layer. In various embodiments, the gate dielectric layer may include a fluoride- or chloride-based compound, such as calcium fluoride (CaF2).

Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs) and bias circuitry. The one or more FETs may transition between an off state and an on state to facilitate switching of a transmission signal. The one or more FETs may include a drain terminal, a source terminal, a gate terminal, and a body. The biasing circuitry may bias the drain terminal and the source terminal to a first DC voltage in the on state and a second DC voltage in the off state. The first and second DC voltages may be non-negative. The biasing circuitry may be further configured to bias the gate terminal to the first DC voltage in the off state and the second DC voltage in the on state.

Abstract: Embodiments include but are not limited to apparatuses and systems including a die or a preform including at least one groove configured to extend from at least one via of the die to an edge of the die. Other embodiments may be described and claimed.

Abstract: Embodiments of the present disclosure flip-chip packaging techniques and configurations. An apparatus may include a package substrate having a plurality of pads formed on the package substrate, the plurality of pads being configured to receive a corresponding plurality of interconnect structures formed on a die and a fluxing underfill material disposed on the package substrate, the fluxing underfill material comprising a fluxing agent configured to facilitate formation of solder bonds between individual interconnect structures of the plurality of interconnect structures and individual pads of the plurality of pads and an epoxy material configured to harden during formation of the solder bonds to mechanically strengthen the solder bonds. Other embodiments may also be described and/or claimed.

Abstract: Various embodiments may provide a circuit including a radio frequency (RF) power amplification module having an RF power amplifier. The RF power amplification module may further include a directional coupler coupled with the RF power amplifier and configured to produce a power signal at a coupling port of the directional coupler corresponding to an output power of the RF power amplifier. The RF power amplification module may further include a switch coupled between the coupling terminal and a sensing path to selectively couple the coupling port with a power detector via the sensing path. The RF power amplification module may further include a termination load coupled to an isolation port of the directional coupler. Some embodiments may include a plurality of RF power amplification modules coupled together by the sensing path.

Abstract: A bulk acoustic wave resonator comprising a substrate, a Bragg reflector, a top and a bottom electrode and a piezoelectric layer with means for suppression of the pass-band ripples in a bulk acoustic wave filter. The means for absorbing or scattering the spurious modes are a roughened rear side of the substrate, an absorbing layer disposed on the rear side of the substrate and/or an absorbing layer disposed on the front side of the substrate.

Abstract: A wafer level package includes an epoxy layer formed on an adhesive covered substrate during manufacturing for securing electrical components in place prior to being embedded in a molded material. An electrically conductive block is fixed in the epoxy layer. Vias are formed for accessing face up component contacts using a metalized layer on the surface of the molded material. After stripping the adhesive and substrate, the epoxy layer is penetrated to expose electrical contacts for face down components. An electrical connection is made between the face up and face down components using the block. Optionally, a dielectric layer covers the molded material and a second metalized layer placed on the dielectric layer to carry another electrical component embedded in a second dielectric layer covering the first dielectric layer. Thus a stacked component arrangement including multiple die and passive components is effectively fabricated into the wafer level package.

Abstract: Embodiments of apparatuses, systems and methods relating to a mixer having high second- and third-order intercept points are disclosed. Other embodiments may be described and claimed.

Abstract: Embodiments provide a multi-stage radio frequency (RF) power amplifier (PA) having a low dynamic error vector magnitude (EVM). A first stage of the RF PA may include a first active device configured to receive an enable signal and to turn on in response to the enable signal, thereby activating the first stage. The RF PA may further include a second active device coupled in series with the first active device and configured to receive a main supply voltage. The second active device may provide a first supply voltage across the first active device that is less than and independent of the main supply voltage. One of the first active device or the second active device may be configured to receive an RF input signal and to pass an amplified RF output signal to a second stage of the RF PA circuit.

Abstract: Embodiments provide a switching device including one or more field-effect transistors (FETs) and bias circuitry. The one or more FETs may transition between an off state and an on state to facilitate switching of a transmission signal. The one or more FETs may include a drain terminal, a source terminal, a gate terminal, and a body. The biasing circuitry may bias the drain terminal and the source terminal to a first DC voltage in the on state and a second DC voltage in the off state. The first and second DC voltages may be non-negative. The biasing circuitry may be further configured to bias the gate terminal to the first DC voltage in the off state and the second DC voltage in the on state.

Abstract: Embodiments of circuits, methods and systems for a voltage-controlled current source are disclosed. In some embodiments, the voltage-controlled current source may be a three-terminal device having separated gate structures. Other embodiments may also be described and claimed.