Abstract: Disclosed embodiments include a direct current to direct current (DC-DC) converter including one or more charge pumps and configured to receive an input voltage and a first clock signal and a second clock signal. The first clock signal and second clock signal may be non-overlapping, and each may alternate between a ground voltage and a first voltage. The DC-DC converter may be configured to produce an output voltage over the clock cycle that has a negative polarity with a magnitude substantially equal to a sum of magnitudes of the input voltage and an integer multiple of the first voltage, the integer multiple being equal to a number of the one or more charge pumps in the DC-DC converter.

Abstract: Embodiments of circuits, devices, and methods related to calibration circuits are disclosed. In various embodiments, a calibration circuit may be used for calibrating a power detector circuit. In various other embodiments, a calibration circuit may be used for calibrating a resistor module. Other embodiments may also be described and claimed.

Abstract: Embodiments of circuits, apparatuses, and systems for a flip-chip power amplifier and impedance matching network are disclosed. Other embodiments may be described and claimed.

Abstract: A surface acoustic wave device with improved temperature characteristics includes a piezoelectric substrate of a single crystal of symmetry 3m, providing propagation of a SAW having an electromechanical coupling factor exceeding 5%, an electrode pattern on a substrate surface forming a resonator, and a SiOx overlay covering the electrode pattern. An optimized thickness of the electrodes combined with an SiOx overlay provide improved performance in RF applications with improved temperature characteristics. To suppress spurious responses the SiOx thickness is varied depending upon the relative thickness and period of the electrodes. The electrode pattern forms resonators with the silicon oxide thickness over the electrodes inversely related to the period of the electrodes of the resonators.

Abstract: An acoustic wave device operable as a piston mode wave guide includes electrodes forming an interdigital transducer on a surface of the piezoelectric substrate, wherein each of the plurality of electrodes is defined as having a transversely extending center region and transversely opposing edge regions for guiding an acoustic wave longitudinally through the transducer. A Silicon Oxide overcoat covers the transducer and a Silicon Nitride layer covers the Silicon Oxide overcoat within only the center and edge regions. The thickness of the Silicon Nitride layer is sufficient for providing a frequency modification to the acoustic wave within the center region and is optimized with a positioning of a Titanium strip within each of the opposing edge regions. The Titanium strip reduces the acoustic wave velocity within the edge regions with the velocity in the edge regions being less than the wave velocity within the transducer center region.

Abstract: Embodiments of a microelectronic package are generally described herein. A microelectronic package may include a die having a first side and a second side, opposite the first side, a flange coupled to the first side of the die, and a lead frame proximately positioned relative to the die and coupled to the second side of the die. Other embodiments may be described and claimed.

Abstract: Embodiments include but are not limited to apparatuses and systems including a quadrature lattice matching network including first path having a series inductor and a shunt inductor, and a second path having a series capacitor and a shunt capacitor. Other embodiments may be described and claimed.

Abstract: An apparatus and method for reducing delamination of an integrated circuit module is disclosed. The integrated circuit module includes a laminate substrate. The integrated circuit module further includes an integrated circuit die operably coupled with the laminate substrate and a plastic semiconductor package overmolded with the laminate substrate. The laminate substrate includes a die attach pad including a plurality of metal oxide regions and non-oxidized metal regions disposed on the die attach pads.

Abstract: An apparatus and method is disclosed for providing an electrostatic discharge protection circuit for compound semiconductor devices and circuits. The electrostatic discharge protection circuit comprises a first terminal and a second terminal. The electrostatic discharge protection circuit further comprises a transistor shunt element that is operably coupled between the first terminal and the second terminal; the transistor shunt element is capable of providing a bi-directional discharge path between the first terminal and the second terminal. The electrostatic discharge protection circuit further comprises a shut-off element that is operably coupled with the second terminal; the shut-off element is capable of keeping the transistor shunt element turned-off.

Abstract: Embodiments of circuits, apparatuses, and systems for a voltage regulator with a control loop for avoiding hard saturation are disclosed. Other embodiments may be described and claimed.

Abstract: Embodiments of circuits, apparatuses, and systems for a quadrature hybrid circuit are disclosed. Other embodiments may be described and claimed.

Abstract: Embodiments of apparatuses, systems and methods relating to a flux-coupled transformer for power amplifier output matching are disclosed. Other embodiments may be described and claimed.

Abstract: Embodiments of circuits, methods and systems for a voltage-controlled current source are disclosed. In some embodiments, the voltage-controlled current source may be a three-terminal device having separated gate structures. Other embodiments may also be described and claimed.

Abstract: Embodiments of circuits, devices, and methods related to a radio frequency switch are disclosed. In various embodiments, a circuit may comprise a series path including a series transistor to be switched on during a first mode of operation; a shunt path including a shunt transistor to be switched off during the first mode of operation; and a return path including a return transistor to be switched on during the first mode of operation. Other embodiments may also be described and claimed.

Abstract: Embodiments of circuits, methods and systems for powering various stages of a logic circuit are disclosed. Other embodiments may also be described and claimed.

Abstract: Embodiments of circuits, apparatuses, and systems for a matching network having a switchable capacitor bank are disclosed. Other embodiments may be described and claimed.

Abstract: Disclosed embodiments include a high electron mobility transistor (HEMT) with an indium gallium nitride layer set as one of a plurality of barrier sublayers and methods for forming such a HEMT. Other embodiments are also be described and claimed.

Abstract: A piezoelectric layer is coupled to a bottom electrode in a method of fabricating a piezoelectric resonator. A bottom metal layer of a top electrode is deposited on the piezoelectric layer. The bottom metal layer is patterned and etched. A top metal layer of the top electrode is deposited on the etched bottom metal layer. The top metal layer is patterned and etched. An interconnect metal layer is deposited on the etched top metal layer and the piezoelectric layer such that the interconnect metal layer isolates the bottom metal layer from subsequent etch steps.

Abstract: An RF system includes a power amplifier with output impedance and a BAW filter with an input impedance and output impedance. A matching network includes an inductance connecting the power amplifier to the BAW filter and an impedance transformation ratio of at least 1:10 is provided at the output impedance of the power amplifier to the output impedance of the BAW filter.

Abstract: A heterojunction bipolar transistor (HBT) device and system having electrostatic discharge ruggedness, and methods for making the same, are disclosed. An HBT device having electrostatic discharge ruggedness may include one or more emitter fingers including an emitter layer, a transition layer formed over the emitter layer, and an emitter cap layer formed over the transition layer.