Abstract: A nonvolatile memory device comprises a substrate, a gate electrode, a single charge trapping sidewall and a source/drain region. The gate electrode is disposed on and electrically isolated from the substrate. The single charge trapping sidewall is disposed adjacent to a sidewall of the gate electrode and electrically isolated from the substrate and the gate electrode, so as to form a non-straight angle between the substrate and the single charge trapping sidewall. The source/drain region is disposed in the substrate and adjacent to the gate electrode.

Abstract: A method for fabricating a microelectromechanical system (MEMS) device of the present invention includes the following steps: providing a substrate, comprising a circuit region and a MEMS region separated from each other; forming an interconnection structure on the substrate in the circuit region, and simultaneously forming a plurality of dielectric layers and a first electrode on the substrate in the MEMS region, wherein the first electrode comprises at least two metal layers formed in the dielectric layers and a protection ring formed in the dielectric layers and connecting two adjacent metal layers, so as to define an enclosed space between the two adjacent metal layers; forming a second electrode on the first electrode; and removing the dielectric layers outside the enclosed space in the MEMS region to form a cavity between the electrodes.

Abstract: A stacked electrostatic discharge (ESD) protection device includes a substrate; a deep well with a first conductive type formed in the substrate, the deep well defining a plurality of element regions with a second conductive type therein; and a plurality of ESD protection elements, each of which is formed in one of the element regions. A current path is formed by connecting the plurality of ESD protection elements in series.

Abstract: A method for manufacturing a FinFET includes forming a merging spacer, through a plurality of sidewall pattern-transferring processes, and modifying a first interval between adjacent first mandrels as shorter than twice of thicknesses of a nitride layer, which is formed on the first mandrels and contoured thereto, followed by a first spacer being formed on a sidewall thereof, so that a FinFET composed of a plurality of fin-shaped structures having a non-integral multiple of pitches as well as an integral multiple of pitches can be manufactured.

Abstract: A clock transmission adjusting method applied to integrated circuit design is provided. The clock transmission adjusting method includes the following steps. At first, a timing path including a clock source and a sequential logic cell is provided. Then, at least one non-active wire delay module is inserted in the timing path to approach a predetermined clock arrival time. An integrated circuit structure utilizing the clock transmission adjusting method is also provided.

Abstract: A method for manufacturing a finFET device is provided. Firstly, a first multiple layer structure and a second multiple layer structure are formed on a substrate in sequence. Then, a first sacrificial pattern is formed on the second multiple layer structure. A first spacer is next formed on a sidewall of the first sacrificial pattern. Subsequently, a portion of the second multiple layer structure is etched so as to form a second sacrificial pattern by using the first spacer as a hard mask. Next, a second spacer is formed on a sidewall of the second sacrificial pattern. After that, the first multiple layer structure is patterned by using the second spacer as a hard mask. Finally, the substrate is etched so as to form at least a first fin structure by using the patterned first multiple layer structure as a hard mask.

Abstract: An interposer structure including a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. The shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface. The deep trenches extend from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface. The metal damascene structures are filled in both of the shallow trenches and the deep trenches. A manufacturing method for the aforementioned interposer structure is also provided.

Abstract: A semiconductor process is described in this application. The process includes the following steps: providing a semiconductor substrate; measuring a warpage level of the semiconductor substrate; and holding the semiconductor substrate by providing at least one vacuum suction according to the warpage level, so that the semiconductor substrate is subjected to a plurality of varied suction intensities. The semiconductor substrate is held on a chuck having a plurality of holes grouped into a plurality of groups, and the sizes of the holes within different groups are different, wherein the sizes of the holes increase from a center toward an edge of the chuck, and the holes are arranged in a spiral.

Abstract: An etching method for manufacturing MEMS devices is provided. The method includes steps of: providing a substrate including a first surface and a second surface opposite to the first surface, wherein a base structure, a sacrificial structure and at least one adhesion layer are arranged on the first surface of the substrate, the adhesion layer is disposed between the base structure and the sacrificial structure, the base structure is disposed between the adhesion layer and the substrate; performing a surface grinding process on the second surface of the substrate; performing a first plasma etching process by using a first mixed gas to remove the sacrificial structure, wherein the first mixed gas includes oxygen and a first nitrogen-based gas; and performing a second plasma etching process by using a second mixed gas to remove the adhesion layer, wherein the second mixed gas includes a second nitrogen-based base gas and a fluorine-based gas.

Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

Abstract: A memory cell array includes a bit line, a complementary bit line, a first operation voltage supply circuit, a second operation voltage supply circuit, a first memory cell and a second memory cell. The first operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a first operation voltage. The second operation voltage supply circuit is electrically coupled to the bit line and the complementary bit line and used for supplying a second operation voltage. The first memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the first operation voltage. The second memory cell is electrically coupled to the bit line and the complementary bit line and used for receiving the second operation voltage. The first and second memory cells are located in a same column in the memory cell array.

Abstract: A manufacturing process of an etch stop layer is provided. The manufacturing process includes steps of providing a substrate; forming a gate stack structure over the substrate, wherein the gate stack structure at least comprises a dummy polysilicon layer and a barrier layer; removing the dummy polysilicon layer to define a trench and expose a surface of the barrier layer; forming a repair layer on the surface of the barrier layer and an inner wall of the trench; and forming an etch stop layer on the repair layer. In addition, a manufacturing process of the gate stack structure with the etch stop layer further includes of forming an N-type work function metal layer on the etch stop layer within the trench, and forming a gate layer on the N-type work function metal layer within the trench.

Abstract: A method for fabricating an image sensor, wherein the method comprises steps as follows: Firstly, a transparent substrate is formed on a working substrate. Pluralities of micro lens are formed in the transparent substrate, wherein the lenses have a refraction ratio differing from that of the transparent substrate. Subsequently, a color filter is formed on the lenses. Afterward, the color filter is engaged with an image sensing device by flipping around the working substrate.

Abstract: An integrated semiconductor device and method for fabricating the same are provided wherein the integrated semiconductor device comprises a substrate a first stress-inducing layer, a second stress-inducing layer and an integrated circuit layer. The first stress-inducing layer covers on the substrate. The second stress-inducing layer partially covers on the first stress-inducing layer. The integrated circuit layer is bonded over the substrate.

Abstract: A LDMOS structure including a semiconductor substrate, a drain region, a lightly doped drain (LDD) region, a source region and a gate structure is provided. The substrate has a trench. The drain region is formed in the semiconductor substrate under the trench. A LDD region is formed in the semiconductor substrate at a sidewall of the trench. The source region is formed in the semiconductor substrate. The gate structure is formed on a surface of the semiconductor substrate above the LDD region between the drain region and the source region. A method for manufacturing the LDMOS structure is also provided.

Abstract: A method for planarizing semiconductor devices, wherein the method comprises steps as follows: At least one patterned metal layer is formed on a substrate. A material layer having a first area and a second area is provided on the patterned metal layer and the substrate, in which there is a step height existing between the first area and the second area. A first polishing process having a first selection ratio of relative speeds for removing the material layer at the first area to that at the second area is then performed on the material layer. Subsequently, a second polishing process having a second selection ratio of relative speeds for removing the material layer at the first area to that at the second area is performed on the material layer, and the second selection ratio is greater than the first selection ratio.

Abstract: A method for manufacturing the MIM capacitor structure is provided. A first damascene electrode layer is formed in the first opening formed in a first dielectric layer. An insulating barrier layer is formed to cover the first dielectric layer and the first damascene electrode layer. A second opening and a third opening are formed in the second dielectric layer formed on the insulating barrier layer. The second opening and the third opening are located above the first damascene electrode layer to expose a portion of the insulating barrier layer therefrom. The insulating barrier layer in the third opening is removed to expose a portion of the first damascene electrode layer. A second damascene electrode layer is formed in the second opening to be contacted with the insulating barrier layer and a dual damascene structure is formed in the third opening to be contacted with the first damascene electrode layer.

Abstract: A semiconductor electrostatic discharge (ESD) protection apparatus comprises at least one elementary transistor with a first conductivity type, a well region with a second conductivity type, a guard ring with the second conductivity type and a semiconductor interval region. The elementary transistor is formed in the well region. The guard ring surrounds the at least one elementary transistor. The semiconductor interval region is disposed between the elementary transistor and the guard ring in order to surrounds the elementary transistor, wherein the semiconductor interval region is an undoped region, a doped region with the first conductivity type or a doped region with the second conductivity type that has a doping concentration substantially less than that of the well region.

Abstract: A circuit structure of a test-key and a test method thereof are provided. The circuit structure comprises a plurality of transistors, a first conductive contact, a plurality of second conductive contacts and a plurality of third conductive contacts. The transistors are arranged in a matrix. The first conductive contact is electrically connected to one source/drain of each transistor in each column of the matrix. Each second conductive contact is electrically connected to the other source/drain of each transistor in a corresponding column of the matrix. Each third conductive contact is electrically connected to the gate of each transistor in a corresponding row of the matrix. In the method, a plurality of driving pulses are provided to the third conductive contacts in sequence, and a plurality of output signals are read from the second conductive contacts to perform an element-character analyzing operation when a row of the transistors is turned on.

Abstract: An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof.