Abstract: A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer.

Abstract: A chip with electrostatic discharge protection function includes two power rails, a pin, a P-type FinFET, an N-type FinFET, two Fin-resistors, two diodes and an ESD unit. The pin is electrically connected to one power rail sequentially through one Fin-resistor and the P-type FinFET and electrically connected to the other power rail sequentially through the other Fin-resistor and the N-type FinFET. The two FinFETs are configured to have the control terminals thereof for receiving a transmission signal. The pin is further electrically connected to the two power rails through the two diodes, respectively. The ESD unit, electrically connected between the first and second power rails, is configured to provide an ESD path between the first and second power rails.

Abstract: A method for forming a damascene opening, wherein the method comprises steps as follows: Firstly, a semiconductor structure comprising an inter-metal dielectric (IMD), a first hard mask layer and a second hard mask layer stacked in sequence is provided, wherein the semiconductor structure has at least one trench extending downwards from the second hard mask layer to the IMD. A plasma treatment is then performed to modify a portion of the first hard mask layer exposed from the trench. Subsequently, a wet treatment is performed to remove the second hard mask layer and a portion of the first hard mask layer, wherein the plasma-modified portion of the first patterned hard mask layer has a first removing rate substantially less than a second removing rate of the second hard mask layer in the wet treatment.

Abstract: A temperature sensor includes a signal delaying apparatus, a comparison apparatus, a multiplier and a counting apparatus. The signal delaying apparatus is configured to receive a step signal, perform a phase delay operation on the received step signal according to a temperature degree, and thereby forming a first output signal. The comparison apparatus is configured to receive the first output signal and the step signal, and accordingly output a second output signal. The multiplier is configured to receive the second output signal and a clock signal, and accordingly output a third output signal. The counting apparatus is configured to receive the third output signal, count the number of pulses of the third output signal, and generate a digital code accordingly.

Abstract: In a process of forming a seed layer, particularly in a vertical trench or via, a semiconductor substrate having a dielectric structure and a hard mask structure thereon is provided. An opening is formed in the hard mask structure, and a trench or via is formed in the dielectric structure in communication with the opening, wherein an area of the opening is greater than that of an entrance of the trench or via. A seed layer is then deposited in the trench or via through the opening, and then subjected to a reflow process.

Abstract: A clock transmission adjusting method applied to integrated circuit design is provided. The clock transmission adjusting method includes the following steps. At first, a timing path including a clock source and a sequential logic cell is provided. Then, at least one non-active wire delay module is inserted in the timing path to approach a predetermined clock arrival time. An integrated circuit structure utilizing the clock transmission adjusting method is also provided.

Abstract: An interposer structure including a semiconductor substrate, a plurality of shallow trenches, a plurality of deep trenches and a plurality of metal damascene structures is provided. The semiconductor substrate has a first surface and a second surface opposite to each other. The shallow trenches are formed on the first surface in both of a first area and a second area of the semiconductor substrate and correspondingly a plurality of respective openings are formed on the first surface. The deep trenches extend from at least one of the shallow trenches toward the second surface in the second area and correspondingly a plurality of respective openings are formed on the second surface. The metal damascene structures are filled in both of the shallow trenches and the deep trenches. A manufacturing method for the aforementioned interposer structure is also provided.

Abstract: A vertical transistor device comprises a substrate, a first source, a drain, a first gate dielectric layer, a first gate electrode and a first doping region. The substrate has at least one protruding portion. The first source having a first conductivity type is formed on the substrate. The drain having the first conductivity type is disposed on the protruding portion. The first gate electrode is disposed adjacent to a first sidewall of the protruding portion. The first gate dielectric layer is disposed between the first gate electrode and the first sidewall as well as being disposed adjacent to the first source and the drain. The first doping region having a second conductivity type is formed beneath the protruding portion and adjacent to the first source.

Abstract: A voltage regulator circuit includes a plurality of transistors and a control circuit. Each transistor has two source/drain terminal and a gate terminal. One source/drain terminal of each transistor is electrically coupled to a source voltage, and the other source/drain terminals of the transistors are electrically coupled to each other and corporately referred to as an output terminal of the voltage regulator circuit. The control circuit is electrically coupled to the gate terminals of the transistors and configured to determine the number of the transistors to be turned on according to the difference between the voltage at the output terminal and a predetermined reference voltage.

Abstract: A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.

Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.

Abstract: A method for fabricating a semiconductor device is provided. The method includes the following steps. Firstly, a substrate having a nitride layer and a platinum (PO-containing nickel (Ni)-semiconductor compound layer is provided. Then the nitride layer and the Pt are removed in situ with a chemical solution including a sulfuric acid component and a phosphoric acid component.

Abstract: A method for manufacturing a non-volatile memory is disclosed. A gate structure is formed on a substrate and includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer is partly removed, thereby a symmetrical opening is formed among the gate conductive layer, the substrate and the gate dielectric layer, and a cavity is formed on end sides of the gate dielectric layer. A first oxide layer is formed on a sidewall and bottom of the gate conductive layer, and a second oxide layer is formed on a surface of the substrate. A nitride material layer is formed covering the gate structure, the first and second oxide layer and the substrate and filling the opening. An etching process is performed to partly remove the nitride material layer, thereby forming a nitride layer on a sidewall of the gate conductive layer and extending into the opening.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes a first dielectric layer, a first damascene electrode layer, an insulating barrier layer, a second dielectric layer and a second damascene electrode layer. The first damascene electrode layer is formed in the first dielectric layer. The insulating barrier layer covers the first dielectric layer and the first damascene electrode layer, and is a single layer structure. The second dielectric layer is formed on the insulating barrier layer. The second damascene electrode layer is formed in the second dielectric layer and is contacted with the insulating barrier layer. The MIM capacitor structure can includes a dual damascene structure formed in the second dielectric layer and the insulating barrier layer and electrically connected to the first damascene electrode layer. A method for manufacturing the MIM capacitor structure is also provided.

Abstract: A method for fabricating an integrated circuit includes the following steps of: providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon; forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure, wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.

Abstract: A programmable memory cell includes a non-volatile memory unit, a reference current generator and a readout unit. The non-volatile memory unit is configured to be performed by a program operation, a read operation or an erase operation. The reference current generator is configured to generate a reference current; wherein a value of the reference current is dynamically modulated according to a count number of the program and erase operations performed on the non-volatile memory unit. The readout unit, electrically coupled to the non-volatile memory unit and the reference current generator, is configured to read a data stored in the non-volatile memory cell according to the reference current. A data read method applied to the aforementioned programmable memory cell is also provided.

Abstract: A pulse width estimation method, applied between an integrated circuit and a circuit system for generating a reference pulse with a predetermined pulse width, includes steps for the following: generating an under-test pulse with an under-test pulse width by the integrated circuit; delivering the under-test and reference pulses to the integrated circuit for multiplying the under-test pulse width and the predetermined pulse width thereof by a timing gain and thereby obtaining a gained under-test pulse and a gained reference pulse, respectively; providing, by the integrated circuit, a count pulse for sampling the gained under-test pulse and the gained reference pulse and thereby obtaining a first count number and a second count number, respectively; and estimating the under-test pulse width by using the predetermined pulse width, the first count number and the second count number. A pulse width estimation device is also provided.

Abstract: A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.

Abstract: An integrated circuit device includes a semiconductor substrate and a first transistor and a second transistor constructed in the semiconductor substrate. The first transistor has a first operating voltage higher than a second operating voltage of a second transistor. The first transistor includes a first drain structure, a first source structure, an isolation structure and a first gate structure. The first source structure includes a high voltage first-polarity well region, a first-polarity body region, a heavily doped first-polarity region, a second-polarity grade region and a heavily doped second-polarity region. The heavily doped second-polarity region is surrounded by the second-polarity grade region. The second-polarity grade region is surrounded by the first-polarity body region. The second transistor includes a second drain structure, a second source structure, a second gate structure and a first-polarity drift region.

Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a first well region, a gate structure, a second well region, a second well region, a second conductive region, and a deep well region. The first well region contains first type conducting carriers. The second well region is disposed within the first well region, and contains second type conducting carriers. The first conductive region is disposed on the surface of the first well region, and contains the second type conducting carriers. The deep well region is disposed under the second well region and the first conductive region, and contacted with the second well region. The deep well region contains the second type conducting carriers.