Patents Assigned to United Microelectronics
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Publication number: 20230025163Abstract: A method of manufacturing a semiconductor structure including the following steps is provided. A substrate is provided. The substrate has a first region and a second region. A stacked structure is formed on the substrate in the first region. The stacked structure includes a first dielectric layer, a charge storage layer, a second dielectric layer, a first conductive layer, and a first hard mask layer. A dielectric material layer is formed on the substrate in the second region. A second conductive layer is formed on the dielectric material layer in the second region. A first patterned photoresist layer is formed. The first hard mask layer exposed by the first patterned photoresist layer and a portion of the dielectric material layer exposed by the first patterned photoresist layer are removed by using the first patterned photoresist layer as a mask.Type: ApplicationFiled: August 17, 2021Publication date: January 26, 2023Applicant: United Microelectronics Corp.Inventors: Wen Wen Gong, Xiaofei Han, Chow Yee Lim, Hong Liao, Jun Qian
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Publication number: 20230027508Abstract: Provided are a resistive random access memory (RRAM) and a manufacturing method thereof. The resistive random access memory includes multiple unit structures disposed on a substrate. Each of the unit structures includes a first electrode, a first metal oxide layer, and a spacer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. The spacer is disposed on sidewalls of the first electrode and the first metal oxide layer. In addition, the resistive random access memory includes a second metal oxide layer and a second electrode. The second metal oxide layer is disposed on the unit structures and is connected to the unit structures. The second electrode is disposed on the second metal oxide layer.Type: ApplicationFiled: August 6, 2021Publication date: January 26, 2023Applicant: United Microelectronics Corp.Inventors: Kai Jiun Chang, Chun-Hung Cheng, Chuan-Fu Wang
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Publication number: 20230020564Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.Type: ApplicationFiled: August 17, 2021Publication date: January 19, 2023Applicant: United Microelectronics Corp.Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
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Patent number: 11557654Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.Type: GrantFiled: October 27, 2021Date of Patent: January 17, 2023Assignee: United Microelectronics Corp.Inventors: Chia-Jung Hsu, Chin-Hung Chen, Chun-Ya Chiu, Chih-Kai Hsu, Ssu-I Fu, Tsai-Yu Wen, Shi You Liu, Yu-Hsiang Lin
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Publication number: 20220415724Abstract: Provided are a multiple-level interconnect structure having a scatterometry test layer and a manufacturing method thereof. The multiple level interconnect structure includes a patterned reflective layer, a bulk reflective layer and a patterned test layer. The patterned reflective layer is disposed on a substrate and includes a first reflective pattern and a second reflective pattern separated from each other. The bulk reflective layer is disposed on the patterned reflective layer. The patterned test layer is disposed on the bulk reflective layer.Type: ApplicationFiled: August 4, 2021Publication date: December 29, 2022Applicant: United Microelectronics Corp.Inventors: Jia Fang Wu, Hsiang-Chieh Yen, Hsu-Sheng Huang, Zhi Jian Wang
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Publication number: 20220415831Abstract: A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.Type: ApplicationFiled: July 22, 2021Publication date: December 29, 2022Applicant: United Microelectronics Corp.Inventors: Purakh Raj Verma, Su Xing
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Publication number: 20220415836Abstract: A semiconductor device, including a first semiconductor substrate and a second semiconductor substrate, is provided. A first bonding structure is located on the first semiconductor substrate and includes a first pad having an elongated shape. A second bonding structure is located on the second semiconductor substrate and includes a second pad having an elongated shape. The first semiconductor substrate is bonded to the second semiconductor substrate by bonding the first bonding structure and the second bonding structure. The first pad is bonded to the second pad, and an extension direction of the first pad is different from an extension direction of the second pad.Type: ApplicationFiled: July 28, 2021Publication date: December 29, 2022Applicant: United Microelectronics Corp.Inventors: Chung-Hsing Kuo, Chun-Ting Yeh, Ming-Tse Lin
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Publication number: 20220415926Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a carrier substrate, a trap-rich layer, a dielectric layer, an interconnect structure, a device structure layer and a circuit structure. The trap-rich layer is disposed on the carrier substrate. The dielectric layer is disposed on the trap-rich layer. The interconnect structure is disposed on the dielectric layer. The device structure layer is disposed on the interconnect structure and electrically connected to the interconnect structure. The circuit structure is disposed on the device structure layer and electrically connected to the device structure layer.Type: ApplicationFiled: July 22, 2021Publication date: December 29, 2022Applicant: United Microelectronics Corp.Inventors: Sheng Zhang, Chunyuan Qi, Xingxing Chen, Chien-Kee Pang
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Publication number: 20220405565Abstract: A digital signal modulation method for a photon artificial intelligence computing chip, including: modulating one or more groups of digital electrical signals into optical signals; where the group of digital electrical signals comprises several timing signals being outputted in sequence in a channel within a fixed period; where each timing signal has the same base clock and signal time length; where each timing signal conveying N-bit digital information has 2N?1 base clocks, the number of the base clocks of a high-level signal or the number of a digital signal “1” in the timing signal is a signal value of the timing signal, and the signal value is equal to a value of the N-bit digital information being transmitted; and where the timing signal is a modulating signal for converting the electrical signal to the optical signal.Type: ApplicationFiled: July 22, 2020Publication date: December 22, 2022Applicant: United Microelectronics Center Co., LtdInventors: Ye TIAN, Yang ZHAO, Wei WANG, Shengping LIU, Qiang LI, Junbo FENG, Jin GUO, Jianzhong HAN
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Publication number: 20220399202Abstract: Provided are a semiconductor device and a manufacturing method thereof. The semiconductor device includes a substrate, a semiconductor device structure, a doped dielectric layer and an interlayer dielectric layer. The substrate has a first surface and a second surface opposite to each other. The semiconductor device structure is disposed on the first surface. The doped dielectric layer is disposed on the second surface. The interlayer dielectric layer is disposed on the doped dielectric layer.Type: ApplicationFiled: July 6, 2021Publication date: December 15, 2022Applicant: United Microelectronics Corp.Inventor: Jingyu Fan
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Publication number: 20220393005Abstract: Provided are a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first metal layer, a second metal layer and a dielectric layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first metal layer is disposed in the second nitride semiconductor layer. The second metal layer is disposed on the second nitride semiconductor layer. The dielectric layer is disposed between the first metal layer and the second nitride semiconductor layer and/or between the second metal layer and the second nitride semiconductor layer.Type: ApplicationFiled: July 21, 2021Publication date: December 8, 2022Applicant: United Microelectronics Corp.Inventors: Chih Tung Yeh, Wen-Jung Liao
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Publication number: 20220392768Abstract: The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.Type: ApplicationFiled: June 7, 2021Publication date: December 8, 2022Applicant: United Microelectronics Corp.Inventors: Yi Jing Wang, Chia-Chang Hsu, Chien-Hao Chen, Chang-Mao Wang, Chun-Chi Yu
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Publication number: 20220384376Abstract: A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. The outer bonding pad pattern includes first bonding pads, the inner bonding pad pattern includes second bonding pads, a density of the first bonding pads is greater than that of the second bonding pads. The first bonding pads of the outer bonding pad pattern is distributed to form a plurality of pad rings surrounding the inner bonding pad pattern, and the first bonding pads of the plurality of pad rings are aligned in a horizontal direction or a vertical direction.Type: ApplicationFiled: August 4, 2022Publication date: December 1, 2022Applicant: United Microelectronics Corp.Inventors: Ming-Tse Lin, Chung-Hsing Kuo, Hui-Ling Chen
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Publication number: 20220382169Abstract: A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.Type: ApplicationFiled: June 21, 2021Publication date: December 1, 2022Applicant: United Microelectronics Corp.Inventors: Min Cheng Yang, Wei Cyuan Lo, Yung-Feng Cheng
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Publication number: 20220384632Abstract: Provided are a nitride semiconductor device and a manufacturing method thereof. The nitride semiconductor device includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a metal layer and a dielectric layer. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a trench. The trench exposes a part of the first nitride semiconductor layer. The metal layer is disposed in the trench. The dielectric layer is disposed in the trench and located between the metal layer and the first nitride semiconductor layer.Type: ApplicationFiled: July 1, 2021Publication date: December 1, 2022Applicant: United Microelectronics Corp.Inventors: Chih Tung Yeh, Wen-Jung Liao
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Publication number: 20220367565Abstract: Provided are a non-volatile memory device and a manufacturing method thereof. The non-volatile memory device includes a substrate having a memory region and a dummy region surrounding the memory region, an interconnect structure, memory cells, conductive vias and dummy vias. The interconnect structure is disposed on the substrate and in the memory region. The memory cells are disposed on the interconnect structure and arranged in an array when viewed from a top view. The memory cells include first memory cells in the memory region and second memory cells in the dummy region. The conductive vias are disposed in the memory region and between the first memory cells and the interconnection structure to electrically connect each of the first memory cells to the interconnect structure. The dummy vias are disposed in the dummy region and surround the memory region.Type: ApplicationFiled: June 11, 2021Publication date: November 17, 2022Applicant: United Microelectronics Corp.Inventors: Cheng-Yi Lin, Tang Chun Weng, Chia-Chang Hsu, Yung Shen Chen, Chia-Hung Lin
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Publication number: 20220367182Abstract: A method for manufacturing a semiconductor device is provided. The method includes a step of performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; surface treatment is performed on the planar surface layer to form a treated planarization layer, and a second silicon oxide layer is formed on the treated planarization layer.Type: ApplicationFiled: June 21, 2021Publication date: November 17, 2022Applicant: United Microelectronics Corp.Inventors: Yu Cheng Lin, Wei-Chuang Lai
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Publication number: 20220359317Abstract: A stress measuring structure, including a substrate, a support layer, a material layer, and multiple marks, is provided. The support layer is disposed on the substrate. The material layer is disposed on the support layer. There is a trench exposing the support layer in the material layer. The material layer includes a main body and a cantilever beam. The trench is located between the cantilever beam and the main body and partially separates the cantilever beam from the main body. One end of the cantilever beam is connected to the main body. The marks are located on the main body and the cantilever beam.Type: ApplicationFiled: June 8, 2021Publication date: November 10, 2022Applicant: United Microelectronics Corp.Inventors: Yu Hsiang Lin, Jing-Yao Kao, En-Kai Dong
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Publication number: 20220344492Abstract: A method of manufacturing a capacitor structure is provided, including the following steps. A substrate is provided. A first doped silicon material layer is formed on the substrate. A surface flattening process is performed on the first doped silicon material layer through a plasma treatment. An insulating material layer is formed on the first doped silicon material layer after the surface flattening process is performed. A second doped silicon material layer is formed on the insulating material layer. The first doped silicon material layer is patterned into a first electrode. The insulating material layer is patterned into an insulating layer. The second doped silicon material layer is patterned into a second electrode. The method of manufacturing the capacitor structure may be used to produce a capacitor with better reliability and may improve capacitance density.Type: ApplicationFiled: May 13, 2021Publication date: October 27, 2022Applicant: United Microelectronics Corp.Inventors: Xiang Li, Ding Lung Chen, Changda Yao
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Publication number: 20220336519Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.Type: ApplicationFiled: May 17, 2021Publication date: October 20, 2022Applicant: United Microelectronics Corp.Inventors: Zhaoyao Zhan, Jing Feng, Qianwei Ding, Xiaohong Jiang, Ching-Hwa Tey
