Patents Assigned to United Microelectronics
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Publication number: 20240014307Abstract: A high electron mobility transistor (HEMT) device and a method of forming the HEMT device are provided. The HEMT device includes a substrate, a channel layer, a barrier layer, and a gate structure. The substrate has at least one active region. The channel layer is disposed on the at least one active region. The barrier layer is disposed on the channel layer. The gate structure is disposed on the barrier layer. The gate structure includes a metal layer and a P-type group III-V semiconductor layer vertically disposed between the metal layer and the barrier layer. The P-type group III-V semiconductor layer includes a lower portion and an upper portion on the lower portion, and the upper portion has a top area greater than a top area of the lower portion.Type: ApplicationFiled: August 16, 2022Publication date: January 11, 2024Applicant: United Microelectronics Corp.Inventors: Wei Jen Chen, Kai Lin Lee
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Publication number: 20240016062Abstract: A method of fabricating an MTJ device is provided including the following process. A first via is formed in the first dielectric layer. A first electrode layer is formed on the first dielectric layer and the first via. An MTJ stack layer is formed on the first electrode layer. A patterned second electrode layer is formed on the MTJ stack layer and used as a mask. A first ion beam etching process is performed to etch the patterned second electrode layer and pattern the MTJ stack layer and the first electrode layer to form a second electrode, an MTJ stack structure, and a first electrode. A first protective layer is formed to cover the second electrode and the MTJ stack structure. A second ion beam etching process is performed to remove a portion of the MTJ stack structure and a portion of the first electrode.Type: ApplicationFiled: July 27, 2022Publication date: January 11, 2024Applicant: United Microelectronics Corp.Inventors: Shun-Yu Huang, Yi-Wei Tseng, Chih-Wei Kuo, Yi-Xiang Chen, Hsuan-Hsu Chen, Chun-Lung Chen
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Publication number: 20240012322Abstract: A photomask structure including a layout pattern and at least one assist pattern is provided. The layout pattern includes corners. The assist pattern wraps at least one of the corners. There is a gap between the edge of the layout pattern and the assist pattern.Type: ApplicationFiled: July 31, 2022Publication date: January 11, 2024Applicant: United Microelectronics Corp.Inventors: Chia-Chen Sun, Song-Yi Lin, En-Chiuan Liou
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Publication number: 20240016067Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.Type: ApplicationFiled: August 10, 2022Publication date: January 11, 2024Applicant: United Microelectronics Corp.Inventors: Chih-Wei Kuo, Chung Yi Chiu, Yi-Wei Tseng, Hsuan-Hsu Chen, Chun-Lung Chen
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Publication number: 20240015958Abstract: A one-time programmable memory structure comprises: A transistor includes a gate. A capacitor includes a first electrode, a second electrode, and an insulating layer. The second electrode is disposed on the first electrode. A top surface of the first electrode and a top surface of the gate are located on a same plane perpendicular to a direction of the first electrode toward the second electrode. An interconnect structure is electrically connected between the transistor and the first electrode of the capacitor. The interconnect structure is electrically connected to the first electrode at a top surface of the first electrode. A resistor comprises a conductive layer. Top and bottom surfaces of the conductive layer are respectively located on a same plane, perpendicular to the direction of the first electrode toward the second electrode, with the top and bottom surfaces of the gate.Type: ApplicationFiled: September 20, 2023Publication date: January 11, 2024Applicant: United Microelectronics Corp.Inventors: Kuo-Hsing Lee, Chi-Horn Pai, Chang Chien Wong, Sheng-Yuan Hsueh, Ching Hsiang Tseng, Shih-Chieh Hsu
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Publication number: 20240006345Abstract: A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.Type: ApplicationFiled: July 27, 2022Publication date: January 4, 2024Applicant: United Microelectronics Corp.Inventors: Po Hsien Chen, Ping-Chia Shih, Che Hao Kuo, Chia-Min Hung, Ching-Hua Yeh, Wan-Chun Liao
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Publication number: 20240006525Abstract: A method for manufacturing a high electron mobility transistor device includes providing a substrate. A channel material, a barrier material, a polarization adjustment material and a conductive material are formed on the substrate. A hard mask layer is formed on the conductive material. The conductive material is patterned to form a conductive layer by using the hard mask layer as a mask. A plurality of protection layers is formed on sidewalls of the hard mask layer and the conductive layer. The polarization adjustment material is patterned to form a polarization adjustment layer by using the plurality of protection layers and the hard mask as masks. The plurality of protection layers is removed. A portion of the conductive layer is laterally removed to form a first gate conductive layer.Type: ApplicationFiled: July 21, 2022Publication date: January 4, 2024Applicant: United Microelectronics Corp.Inventors: Yuan Yu Chung, Bo-Yu Chen, You-Jia Chang, Lung-En Kuo, Kun-Yuan Liao, Chun-Lung Chen
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Patent number: 11862727Abstract: The invention provides a method for fabricating a fin structure for fin field effect transistor, including following steps. Providing a substrate, including a fin structure having a silicon fin and a single mask layer just on a top of the silicon fin, the single mask layer being as a top portion of the fin structure. Forming a stress buffer layer on the substrate and conformally covering over the fin structure. Performing a nitridation treatment on the stress buffer layer to have a nitride portion. Perform a flowable deposition process to form a flowable dielectric layer to cover over the fin structures. Annealing the flowable dielectric layer. Polishing the flowable dielectric layer, wherein the nitride portion of the stress buffer layer is used as a polishing stop.Type: GrantFiled: December 29, 2022Date of Patent: January 2, 2024Assignee: United Microelectronics Corp.Inventors: Hao Che Feng, Hung Jen Huang, Hsin Min Han, Shih-Wei Su, Ming Shu Chiu, Pi-Hung Chuang, Wei-Hao Huang, Shao-Wei Wang, Ping Wei Huang
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Patent number: 11864473Abstract: Provided is a resistive random-access memory device, including a dielectric layer located on a substrate, a first electrode which is a column located on the dielectric layer, a second electrode covering a top surface and a sidewall of the first electrode, and a variable resistance layer sandwiched between the top surface of the first electrode and the second electrode and between the sidewall of the first electrode and the second electrode and located between the second electrode and the dielectric layer.Type: GrantFiled: August 17, 2021Date of Patent: January 2, 2024Assignee: United Microelectronics Corp.Inventors: Wen-Jen Wang, Chun-Hung Cheng, Chuan-Fu Wang
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Patent number: 11855156Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.Type: GrantFiled: June 30, 2022Date of Patent: December 26, 2023Assignee: United Microelectronics Corp.Inventors: Chih-Jung Chen, Yu-Jen Yeh
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Publication number: 20230408900Abstract: A method for forming a photomask is provided. The method includes: providing a photomask pattern for a target pattern; obtaining a first light intensity curve according to the photomask pattern by simulation; subjecting the first light intensity curve to a check on light intensities at pattern edges of the target pattern to define a light intensity error; retargeting the photomask pattern to reduce the light intensity error; identifying a lithography weak region in the target pattern; obtaining a second light intensity curve of the lithography weak region by simulation; subjecting the second light intensity curve to a check on a peak light intensity to define a peak intensity error; retargeting the target pattern to reduce the peak intensity error; and retargeting the photomask pattern again based on the modified target pattern.Type: ApplicationFiled: July 26, 2022Publication date: December 21, 2023Applicant: United Microelectronics Corp.Inventor: Pin Han Huang
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Publication number: 20230411308Abstract: Provided is a semiconductor structure including a first and a second conductive layers, and a first group of vias. The second conductive layer is disposed on the first conductive layer. The first group of vias is disposed between and connects the first and the second conductive layer. The first group of vias includes a first, a second, a third and a fourth vias. The first and second vias are arranged in a first column. The third and fourth vias are arranged in a second column. The first via is adjacent to the third via. The second via is adjacent to the fourth via. The extension directions of the first and second vias are orthogonal to each other, the extension directions of the third and the fourth vias are orthogonal to each other, and the extending directions of the first and the third vias are orthogonal to each other.Type: ApplicationFiled: July 14, 2022Publication date: December 21, 2023Applicant: United Microelectronics Corp.Inventors: Chia-Chen Sun, En-Chiuan Liou
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Publication number: 20230411343Abstract: Provided is a manufacturing method of a semiconductor structure. The manufacturing method includes the following steps. A first dielectric layer is formed on a first substrate. A second dielectric layer is formed on a second substrate. A first heat treatment is performed on the first dielectric layer and the second dielectric layer, wherein a temperature of the first heat treatment is between 300° C. and 400° C. A first conductive via is formed in the first dielectric layer. A second conductive via is formed in the second dielectric layer. The first substrate and the second substrate are bonded in a manner that the first dielectric layer faces the second dielectric layer, so as to connect the first conductive via and the second conductive via.Type: ApplicationFiled: August 8, 2022Publication date: December 21, 2023Applicant: United Microelectronics Corp.Inventors: Sheng Zhang, Kai Zhu, Chien-Kee Pang, Chia-Liang Liao
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Patent number: 11849649Abstract: A method for fabricating memory cell of magnetoresistive RAM includes forming a memory stack structure on a first electrode layer. The memory stack structure includes a SAF layer to serve as a pinned layer; a magnetic free layer and a barrier layer sandwiched between the SAF layer and the magnetic free layer. A second electrode layer is then formed on the memory stack structure. The SAF layer includes a first magnetic layer, a second magnetic layer, and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first and second magnetic layers, and the second metal element of the first magnetic layer and the second magnetic layer interfaces with the spacer layer.Type: GrantFiled: January 12, 2022Date of Patent: December 19, 2023Assignee: United Microelectronics Corp.Inventors: Da-Jun Lin, Bin-Siang Tsai, Ting-An Chien
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Publication number: 20230402537Abstract: A high electron mobility transistor (HEMT) device includes a substrate, a channel layer, a source, a drain, a buffer layer, and a plurality of amorphous regions. The channel layer is located above the substrate. The source is located on the channel layer. The drain is located on the channel layer. The buffer layer is located between the substrate and the channel layer. The plurality of amorphous regions are located in the buffer layer below the source and the drain.Type: ApplicationFiled: July 13, 2022Publication date: December 14, 2023Applicant: United Microelectronics Corp.Inventors: Huai-Tzu Chiang, Kai Lin Lee, Zhi-Cheng Lee, Chuang-Han Hsieh
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Publication number: 20230400759Abstract: A photomask design correction method is provided. The photomask design correction method includes the following steps. A layer information data is provided. An OPC process is performed on the layer information data to obtain a first photomask data. A photomask is fabricated based on the first photomask data. A pattern information data of the photomask is obtained after the photomask is fabricated. The difference between the pattern information data and a database of the OPC process is analyzed. An OPC model of the OPC process is corrected based on the difference to obtain a corrected OPC model. The OPC process is performed using the corrected OPC model on the layer information data to obtain a second photomask data.Type: ApplicationFiled: June 9, 2022Publication date: December 14, 2023Applicant: United Microelectronics Corp.Inventors: Min Cheng Yang, Wei Cyuan Lo, Yung-Feng Cheng
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Patent number: 11839160Abstract: The present disclosure provides a flexible integrated array sensor and manufacturing methods thereof. The array sensor includes a silicon wafer, a readout circuit layer, a sensing array layer, and a polymer substrate layer disposed on the silicon wafer. The manufacturing method includes: preparing a silicon wafer; fabricating a plurality of function arrays, each including m*n function units, on a surface of the silicon wafer; etching one or more deep grooves on the surface of the silicon wafer between the arrays; fabricating a thinning support; and thinning a bottom surface of the silicon wafer to a target thickness so that the arrays are separated from each other. The etching depth for etching the one or more deep grooves is equal to or greater than the thickness of the silicon wafer after thinning.Type: GrantFiled: December 4, 2020Date of Patent: December 5, 2023Assignee: United Microelectronics Center Co., LtdInventors: Miao Wang, Weimong Tsang, Wenlong Jiao, Haopeng Wang, Ruifeng Yang
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Publication number: 20230380154Abstract: A structure of memory device includes an active region in a substrate, a dielectric layer on the active region, and a floating gate disposed on the dielectric layer. The active region extends along a first direction in a top-view. The floating gate includes a first protruding structure extending along the first direction from a sidewall of the floating gate protruding from a top surface of the substrate. The whole of the first protruding structure is located in the active region.Type: ApplicationFiled: August 4, 2023Publication date: November 23, 2023Applicant: United Microelectronics Corp.Inventors: Liang Yi, Zhiguo Li, Chi Ren, Qiuji Zhao, Boon Keat Toh
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Publication number: 20230369460Abstract: Provided are a semiconductor structure and a manufacturing method thereof. The manufacturing method of the semiconductor structure includes the following. A gate structure is formed on a substrate. A tilt implanting process is performed to implant group IV elements into the substrate to form a doped region, and the doped region is located on two sides of the gate structure and partially located under the gate structure. A part of the substrate on two sides of the gate structure is removed to form a first recess. A cleaning process is performed on the surface of the first recess. A wet etching process is performed on the first recess to form a second recess. A semiconductor layer is formed in the second recess.Type: ApplicationFiled: June 9, 2022Publication date: November 16, 2023Applicant: United Microelectronics Corp.Inventors: Kuang-Hsiu Chen, Wei-Chung Sun, Chao Nan Chen, Chun-Wei Yu, Kuan Hsuan Ku, Shao-Wei Wang
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Patent number: 11818966Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes a substrate having a pillar protruding from a surface of the substrate, a gate surrounding a part of a side surface of the pillar, a gate dielectric layer, a first electrode, a second electrode, a variable resistance layer, a first doped region and a second doped region. The gate dielectric layer is disposed between the gate and the pillar. The first electrode is disposed on a top surface of the pillar. The second electrode is disposed on the first electrode. The variable resistance layer is disposed between the first electrode and the second electrode. The first doped region is disposed in the pillar below the gate and in a part of the substrate below the pillar. The second doped region is disposed in the pillar between the gate and the first electrode.Type: GrantFiled: December 3, 2021Date of Patent: November 14, 2023Assignee: United Microelectronics Corp.Inventors: Yi Yu Lin, Po Kai Hsu, Chun-Hao Wang, Yu-Ru Yang, Ju Chun Fan, Chung Yi Chiu
