Abstract: A semiconductor structure including a first substrate, a first conductive layer, and first bonding pads is provided. The first conductive layer is located on the first substrate. The first conductive layer includes a main body portion and an extension portion. The extension portion is connected to the main body portion and includes a terminal portion away from the main body portion. The first bonding pads are connected to the main body portion and the extension portion. The number of the first bonding pads connected to the terminal portion of the extension portion is plural.

Abstract: A memory structure including a substrate, a first doped region, a second doped region, a first gate, a second gate, a first charge storage structure, and a second charge storage structure is provided. The first gate is located on the first doped region. The second gate is located on the second doped region. The first charge storage structure is located between the first gate and the first doped region. The first charge storage structure includes a first tunneling dielectric layer, a first dielectric layer, and a first charge storage layer. The second charge storage structure is located between the second gate and the second doped region. The second charge storage structure includes a second tunneling dielectric layer, a second dielectric layer, and a second charge storage layer. The thickness of the second tunneling dielectric layer is greater than the thickness of the first tunneling dielectric layer.

Abstract: An overlay target that includes a plurality of working zones and a plurality of line segments. The line segments in each of the working zones have a plurality of widths and are parallel to each other.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

Abstract: An overlay target includes a plurality of working zones, a plurality of holes in each of the working zones, and a first layer filling in the plurality of holes. The plurality of holes are not filled up by the first layer, and a plurality of spaces are reserved in the plurality of holes.

Abstract: Provided is a resistive random access memory (RRAM). The resistive random access memory includes a plurality of unit structures disposed on a substrate. Each of the unit structures includes a first electrode, and a first metal oxide layer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. In addition, the resistive random access memory includes a second electrode. The second electrode is disposed on the plurality of unit structures and connected to the plurality of unit structures.

Abstract: A semiconductor device, including a substrate, a first source/drain region, a second source/drain region, and a gate structure, is provided. The substrate has an extra body portion and a fin protruding from a top surface of the substrate, wherein the fin spans the extra body portion. The first source/drain region and the second source/drain region are in the fin. The gate structure spans the fin, is located above the extra body portion, and is located between the first source/drain region and the second source/drain region.

Abstract: A photomask structure having a first region and a second region is provided. The layout pattern density of the first region is smaller than the layout pattern density of the second region. The photomask structure includes a first layout pattern, a second layout pattern, and first assist patterns. The first layout pattern is located in the first region and the second region. The second layout pattern is located in the second region. The second layout pattern is located on one side of the first layout pattern. The first assist patterns are located on the first sidewall of the first layout pattern and separated from each other. The first sidewall is adjacent to the second layout pattern. The first assist patterns are adjacent to a boundary between the first region and the second region. The lengths of two adjacent first assist patterns decrease in the direction away from the boundary.

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: The invention provides a RRAM structure, which includes a substrate, a high voltage transistor, and a RRAM cell. The high voltage transistor includes a drift region, a gate structure, a source region, a drain region, and an isolation structure. The drift region is located in the substrate. The gate structure is located on the substrate and on a portion of the drift region. The source region and the drain region are located in the substrate on two sides of the gate structure. The drain region is located in the drift region. The isolation structure is located in the drift region and between the gate structure and the drain region. The RRAM cell includes a first electrode, a resistive switching layer, and a second electrode sequentially located on the drain region. The RRAM cell is electrically connected to the high voltage transistor.

Abstract: A patterning process is provided. The patterning process comprises the following steps. A material layer is formed on a substrate. An imprinting process is performed on the material layer using an imprint stamp to form a patterned material layer having a plurality of pattern portions. A hard mask layer is formed between adjacent pattern portions. An etching process is performed using the hard mask layer as an etching mask to remove the pattern portions and a part of the substrate. The hard mask layer is removed.

Abstract: A surface acoustic wave (SAW) device including a substrate is provided. Multiple surface acoustic wave elements are disposed on the substrate. A conductive surrounding structure includes: a wall part, disposed on the substrate and surrounding the surface acoustic wave elements; and a lateral layer part, disposed on the wall part. The lateral layer part has an opening above the surface acoustic wave elements. A cap layer covers the lateral layer part and closes the opening.

Abstract: A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.

Abstract: A semiconductor structure including chips is provided. The chips are arranged in a stack. Each of the chips includes a radio frequency (RF) device. Two adjacent chips are bonded to each other. The RF devices in the chips are connected in parallel. Each of the RF devices includes a gate, a source region, and a drain region. The gates in the RF devices connected in parallel have the same shape and the same size. The source regions in the RF devices connected in parallel have the same shape and the same size. The drain regions in the RF devices connected in parallel have the same shape and the same size.

Abstract: A gallium nitride device and a method for manufacturing a high electron mobility transistor are provided. The gallium nitride device includes a substrate, a channel layer disposed on the substrate, a barrier layer disposed on the channel layer, a cap layer disposed on the barrier layer, a gate disposed on the cap layer, a source, a drain, and ohmic sidewall dams. The source and the drain are formed in the cap layer and the barrier layer. Each of the source and the drain has a trench portion, and a contact below the trench portion and protruding into the channel layer. The ohmic sidewall dams are disposed on a sidewall of the trench portion of each of the source and the drain.

Abstract: A semiconductor structure including a substrate and protection structures is provided. The substrate includes a die region. The die region includes corner regions. The protection structures are located in the corner region. Each of the protection structures has a square top-view pattern. The square top-view patterns located in the same corner region have various sizes.

Abstract: Provided is a magnetoresistive random access memory (MRAM) device including a bottom electrode, a magnetic tunnel junction (MTJ) structure, a first spin orbit torque (SOT) layer, a cap layer, a second SOT layer, an etch stop layer, and an upper metal line layer. The MTJ structure is disposed on the bottom electrode. The first SOT layer is disposed on the MTJ structure. The cap layer is disposed on the first SOT layer. The second SOT layer is disposed on the cap layer. The etch stop layer is disposed on the second SOT layer. The upper metal line layer penetrates though the etch stop layer and is landed on the second SOT layer.

Abstract: Provided are a resistive random access memory (RRAM) and a manufacturing method thereof. The resistive random access memory includes multiple unit structures disposed on a substrate. Each of the unit structures includes a first electrode, a first metal oxide layer, and a spacer. The first electrode is disposed on the substrate. The first metal oxide layer is disposed on the first electrode. The spacer is disposed on sidewalls of the first electrode and the first metal oxide layer. In addition, the resistive random access memory includes a second metal oxide layer and a second electrode. The second metal oxide layer is disposed on the unit structures and is connected to the unit structures. The second electrode is disposed on the second metal oxide layer.