Abstract: A test connecting device including testkey and probe card for use in the testing of integrated circuits is provided. This test connecting device features the use of a symmetrical node-potential scheme that can offset the parasite capacitances between the probe pins on the probe card, thus allowing an increase in frequency response of the probe card. The probe card includes at least six probe pins arranged in a row; and correspondingly, the testkey includes at least six test pads for the six probe pins to make electrical contacts with them during the testing while the probe card is coupled to the testkey. This test connecting device can allow a high-frequency output signal to pass therethrough to the test instrument without causing attenuation to the signal. Moreover, the use of the test connecting device can eliminate the need to install additional hardware components, such as frequency dividers or additional stages to ring oscillators.

Abstract: After the formation of a gate oxide layer, a polysilicon layer is formed right away. The polysilicon layer is used for patterning the gate oxide layer. The photolithography and etching processes of forming the buried contact window are combined with the step of removing the gate oxide layer at the periphery circuit region. Then, after the formation of the gate oxide layer at the memory cell region, one thermal oxidation process is performed to form the gate oxide layer at the periphery circuit region.

Abstract: A method for fabricating a shallow trench isolation (STI) structure in a semiconductor substrate. A stop layer is formed on the substrate and a first sacrificial layer is formed on the stop layer. The first sacrificial layer and the stop layer are defined to form an opening on the substrate. A conformal second sacrificial layer with rounded corners is formed on the substrate. The second sacrificial layer, the first sacrificial layer, and a portion of the substrate are anisotropically removed to form a trench in the substrate using the stop layer as a removal stop layer. The substrate is over removed using the stop layer as a mask layer so that spacers of the second sacrificial layer are remained on the substrate to cover portions of sidewalls of the stop layer.

Abstract: A method for forming electrostatic discharge protection devices that includes the steps of forming a transistor, which comprises a gate, a source region, a drain region, on a semiconductor substrate. Then, an insulating layer is formed over the transistor. Next, the insulating layer above the gate is removed, which represents one characteristic of this invention. Subsequently, a photolithographic processing operation is performed to form a photoresist layer over the substrate. The photoresist layer covers the insulating layer above the gate and the drain region while exposing the insulating layer above the source region. Thereafter, using the photoresist layer as a mask, the exposed insulating layer above the source region is removed. Next, the photoresist layer is removed. Finally, a self-aligned silicide processing operation is performed to form a silicide layer over the gate and the source region.

Abstract: This invention provides a flash memory cell structure comprising a semiconductor substrate; a tunneling oxide layer formed above the substrate and having a long narrow top profile; a gate oxide layer formed above the substrate on each side of the tunneling oxide layer; a bottom conductive layer formed above the substrate and surrounded the gate oxide layer; and a stacked gate formed above the tunneling oxide layer, the gate oxide layer and the bottom conductive layer, wherein there is an insulating layer between the stacked gate and the bottom conductive layer for electrically isolating the stacked gate from the bottom conductive layer, and that the stacked gate further comprises a floating gate, a dielectric layer and a control gate.

Abstract: A process for fabricating bottom electrodes for storage capacitors of memory cell units of a DRAM is disclosed. The process employs the use of a protective dielectric layer that serves as an etching shield in the process of fabrication of the capacitor electrode. The HSG-Si layer that substantially increases the surface area of the capacitor electrode can be protected from etching damage, thereby avoiding short-circuiting phenomena found in the conventional fabrication processes. Improved data retention time capability of the DRAM memory cells can thus be obtained utilizing the fabrication process of the invention.

Abstract: An antifuse structure for semiconductor programmable logic devices and the process of fabrication are described. The antifuse structure has its bottom electrically conductive layer featuring sharp corners formed by consumption of the polysilicon material into the sidewall in a thermal oxidation procedure. The sharp corners enhance the intensity of electric field established by a positive bias applied across the top and bottom conductive layers. The sharp corners do not enhance the electric field intensity when a negative bias is applied. This asymmetric conductivity assists in the reduction of the programming voltage as well as the increase of programming speed when the antifuse element is programmed.

Abstract: A method of the invention for inspecting a defect on a translucid film is provided. The method includes an anti-reflective coating (ARC) layer over the translucid film. The anti-reflective coating (ARC) layer prevents inspecting light from penetrating through the ARC layer and reduces the amount of inspecting light refracting through the translucid film. The inspection is performed by generating an inspecting light with a predetermined angle radiating on the ARC layer. The reflecting light message from different regions of the anti-reflective coating (ARC) layer are separately collected. The reflecting light messages are compared die to die to calculate an inspecting result.

Abstract: A split-gate flash memory cell structure comprising a semiconductor substrate having a gate oxide layer already formed thereon. A first gate is then formed over the gate oxide layer, and a cross-section of the first gate contains two corners, one of which is a sharp corner. An insulating dielectric layer is then formed over the first gate. The insulating dielectric has a lens-shaped cross-section located above the sharp corner. Next, a second gate is formed over the insulating dielectric layer, and surrounded the first gate. A first doped region is formed in the substrate below the sharp corner. Then, a second doped region is formed in the substrate located on the other side of the first gate just opposite the first doped region, furthermore, the second doped region is separated from the first gate by a distance. There is a channel region between the first doped region and the second doped region, and the sharp corner of this invention is located above the semiconductor substrate outside the channel region.

Abstract: A method for fabricating flash memory cells having a DDD structure that prevents leakage current during data erasure, that does not require a high temperature drive-in process, and that easily combines with other logic processes. The method for fabricating the flash memory cells utilizes ion implantation through contact windows to establish heavily doped source and drain regions inside previously formed deeply doped source and drain regions to construct the DDD structure.

Abstract: A method of reducing the fringe capacitance between a gate and a substrate in a semiconductor device. A silicon nitride is formed over a substrate with a buffer oxide layer thereon and patterned to form an opening. The buffer oxide layer within the opening is removed and another oxide layer is formed at the same place as a gate oxide layer. A poly-gate is formed at the opening with a wider width than the opening. Thus, a part of the poly-gate at both ends covers a part of the silicon nitride layer. The silicon nitride layer is then removed and leaves the poly-gate as a T-shape with two ends suspended over the substrate. With a large angle, a light dopant is implanted into the substrate under the suspended part of the poly-gate to form a lightly doped region. With another smaller angle, a heavy dopant is implanted into the substrate beside the poly-gate. Therefore, a source/drain is formed.

Abstract: A method of fabricating a buried bit line. An insulating layer is formed on a substrate, a trench is formed within the substrate by patterning the insulating layer and the substrate and then a liner oxide is formed on the trench surface. Then, a first conductive layer is formed on the insulating layer to cover the liner oxide layer and fills the trench. A portion of the first conductive layer is removed, exposing a portion of the liner oxide layer. Next, the exposed liner oxide layer is removed to form a space which, along with the trench, is filled with a second conductive layer on the insulating layer. Ion implantation and annealing is performed to form a shallow junction region in the substrate and the shallow junction region makes contact with the second conductive layer.

Abstract: A split-gate flash memory cell structure comprising a semiconductor substrate having a gate oxide layer already formed thereon. A first gate is then formed over the gate oxide layer, and a cross-section of the first gate contains two corners, one of which is a sharp corner. An insulating dielectric layer is then formed over the first gate. The insulating dielectric has a lens-shaped cross-section located above the sharp corner. Next, a second gate is formed over the insulating dielectric layer, and surrounded the first gate. A first doped region is formed in the substrate below the sharp corner. Then, a second doped region is formed in the substrate located on the other side of the first gate just opposite the first doped region, furthermore, the second doped region is separated from the first gate by a distance. There is a channel region between the first doped region and the second doped region, and the sharp corner of this invention is located above the semiconductor substrate outside the channel region.

Abstract: A method of fabricating split-gate slash memory can define source and drain regions by using a self-alignment process. Thus, the uniformity of the split-gate flash memory performance is better controlled. This method comprises a floating gate oxide layer, a first polysilicon layer and a mask layer formed sequentially over a first type substrate. The mask layer and the first polysilicon layer are patterned to form a floating gate. A photoresist layer is coated over the substrate and then a pattern is defined on the photoresist layer to expose portion of the substrate. Second type ions are implanted into the exposed substrate to form a drain region. Then, the photoresist layer is removed. An insulating layer is formed over the substrate and then is etched back to form spacers on one side of the floating gate. The second type ions are implanted into the substrate to form a source region. The spacers and the mask layer are removed.

Abstract: A flash memory cell structure comprising a semiconductor substrate having a first transistor and a second transistor formed thereon. The first transistor has a stacked gate and a first source/drain regions, wherein the stacked gate further includes a floating gate and a control gate. The control gate is formed above the floating gate. The second transistor is electrically connected in series with the first transistor. The second transistor functions as a select transistor and includes a gate and a second source/drain regions.

Abstract: A method for manufacturing a comb-shaped lower electrode for a DRAM capacitor including the steps of providing a substrate having a transistor and an insulating layer formed thereon, wherein the insulating layer contains a contact window opening exposing a source/drain region of the transistor; then, forming a polysilicon layer over the insulating layer, the contact window opening and the exposed source/drain region; next, forming a hemispherical grain silicon over the polysilicon layer. Thereafter, an oxide layer is formed over the hemispherical grain silicon, and then a silicon nitride layer is formed over the gaps between the hemispherical grain silicon exposing portions of the oxide layer. In the subsequent step, a plurality of hard mask layers are formed over the oxide layer not covered by the silicon nitride layer, and finally the silicon nitride layer, the oxide layer and portions of the polysilicon layer are removed using the hard mask layers to form a plurality of trenches.