Abstract: A method of fabricating a flash memory cell. A spacer is formed on a sidewall of a controlling gate. A self-aligned source/drain region can thus be formed by the formation of the spacer. The tunneling oxide layer is then formed on the source/drain region instead of on the controlling gate. Thus, the tunneling oxide layer is formed with a self-aligned process.

Abstract: A triple well structure for an embedded dynamic random access memory uses an ion implantation performed on a portion of the first conductive type substrate between a second conductive type source and a second conductive type deep well. A first conductive type block region is formed between the second conductive type source and the second conductive type deep well.

Abstract: A method for forming a STI structure is provided. The method contains sequenitially forming a pad oxide layer and a mask layer on a semiconductor substrate. Several trenches in the substrate through the mask layer and the pad oxide layer. The trenches has a wider trench and a narrower trench. A liner oxide layer is formed at each sidewall of the trenches in the substrate. A spacer is formed on each sidewall of the wider trench, in which the narrower trench simultaneously is filled with same insulating material. A conformal polysilicon layer is formed over the substrate, in which the wider trench is not completely filled yet. An insulating plug is formed to fill the wider trench. Using the insulating plug as an etching mask a portion of the polysilicon layer is removed by etching. As a result, a polysilicon pivot sidewall of the remaining polysilicon layer due to etching may occur. The polysilicon pivot sidewall is compensated with polysilicon.

Abstract: An installation for wafer etching that has an additional bias voltage applied to its lower electrode, comprising a central processing unit, a radio frequency generator, a matching box controller, a radio frequency sensor box, a matching box and an etching machine. The central processing unit is connected to the radio frequency generator and the matching box controller for controlling the generation of radio frequency power and the bias voltage provided by the matching box. The radio frequency sensor box receives the radio frequency power and transfers the radio frequency power to the matching box, while a signal is sent to the matching box controller for controlling the bias voltage supplied to the lower electrode. Consequently, the ions can have more kinetic energy resulting in a greater bombarding effect and the formation of polymer on the wafer is limited. Furthermore, the effect of helium loss can be minimized and down time of the etching machine can be greatly reduced.

Abstract: A method for removing a photoresist. A substrate having a wire on the substrate and a flowable oxide layer over the substrate and a patterned photoresist over the flowable oxide layer is provided. A plasma etching step is performed by using an additional gas mixed with oxygen as a source to remove the photoresist layer.

Abstract: A flash memory structure is formed by a method comprising the steps of providing a semiconductor substrate, and then forming a shallow first trench within the substrate. Thereafter, a buried doped region is formed underneath the first trench so that the buried doped region is at a distance from the substrate surface. The buried doped region is one major aspect in this invention that can be applied to the processing of shallow trench isolation and is capable of reducing device area. Next, a deeper second trench is etched in the substrate. The second trench has a greater depth than the depth of the first trench. Subsequently, insulating material is deposited into the first and the second trench, and then a stacked gate structure is formed above the substrate. Later, the surface source region and drain region are formed on two sides of the stacked gate structure. Through thermal operation, the surface source region alternately connects with the buried doped region to form a buried common source region.

Abstract: An anti-microleakage apparatus is used in a sputtering deposition equipment. A metallic object, such as a wafer, is put in a process chamber. A cryo-pump is used to vacuumed the process chamber. A heater to heat up the process chamber to allow a thermal reaction. The heater is movable and is coupled to an inner bellows line, which allows a low pressure gas can be flushed into the process chamber. The anti-microleakage apparatus is formed on the inner bellows line by wrapping the inner bellows line with an outer bellows line. A higher pressure is created between the inner bellows line and the outer bellow line by filling in a gas. A pressure meter is coupled to the outer bellows line so as to monitor the actual pressure of the higher pressure. When microleakage occurs, the information cab obtained by the pressure meter.

Abstract: A wafer inspection tool for determining the cause of broken wafer edges. The wafer inspection tool comprises a circular transparent plate having a profile similar to a wafer. The circular transparent plate further includes a wafer edge notch for aligning with a wafer and a plurality of clamp pin notches showing wafer clamp pin positions of a particular sputtering chamber. The wafer inspection tool is placed on a sputtering chamber in an easily accessible, one for each sputtering chamber. When broken edges are found on a wafer, the cause of the broken wafer can be traced back by overlaying the broken wafer on the transparent plate with their respective wafer edge notches aligned together. Then, the positions of broken edges are compared with the clamp pin notches on the tool. If broken edges of the wafer match the clamp pin notch positions of a particular chamber, the particular chamber that causes the broken edges is found.

Abstract: A method for fabricating a via that uses a hard etching mask for etching the via. A photoresist layer used to pattern the hard etching mask is removed before starting the via etching. The hard etching mask includes a TiN etching mask, a silicon nitride etching mask, and a oxide/TiN etching mask. For each different etching mass, the TiN etching mask is not necessarily removed after etching; the silicon nitride etching mask is removed after etching; the oxide layer in the oxide/TiN etching mask is sacrificial layer.

Abstract: A method of fabricating a non-volatile flash memory device, wherein a gate structure is formed on a substrate. The method includes at least the following steps. The substrate is implanted with first ions to form a source region in the substrate. A tunneling oxide layer is formed on the substrate. A silicon nitride layer is formed on the substrate. The silicon nitride is etched back to form a silicon nitride spacer on the sides of the gate structure. The substrate is implanted with second ions to form a drain region in the substrate. An oxide layer is formed over the substrate and the gate structure. Then, a polysilicon layer is formed on the oxide layer. The gate structure is used as a selection gate, the silicon nitride spacer is used to store electrons, and the polysilicon layer is used as a controlling gate. The flash memory device can free memory cells by from the influences of over-erased effect.

Abstract: A method for avoiding scratching of wafer backs being held by a vacuum to a fetch arm of a stepper machine for insertion into a cassette holder includes releasing the vacuum in the suction head of the fetch are before the wafer enters the cassette holder. The release of vacuum reduces frictional force between the wafer back and the suction head when the wafer accidentally hits the side of the cassette holder. Therefore, the vacuum release method avoids scratching of wafer backs by the suction head of the fetch arm. The invention requires a separate vacuum release controller to release the vacuum in the suction head for a prescribed delaying period after the fetch arm starts moving toward the cassette holder.

Abstract: A method for forming a shallow trench isolation structure. A pad oxide layer is formed over a substrate. A hard mask layer is formed over the pad oxide layer. A portion of the hard mask layer, the pad oxide layer and the substrate is removed to form a trench in the substrate. Insulation material is deposited into the trench to form an insulation plug. The hard mask layer is removed to expose the sidewalls of the insulation plug. Spacers are formed on the exposed sidewalls of the insulation plug. Ions are implanted into the substrate. The pad oxide layer, the spacers and a portion of the insulation plug are removed. Finally, a gate oxide layer thicker in region around the edge of the insulation plug is formed over the substrate by oxidation.

Abstract: The present invention provides a manufacturing method for a poly film with an anti-reflection rough surface is provided. The method comprises steps of, at first, a thin film is formed over a substrate, and a amorphous silicon layer is formed over the thin film. Next, in situ a first annealing procedure is performed over the amorphous silicon layer. The amorphous silicon layer is changed into a polysilicon layer with the anti-reflection rough surface. Next, in situ a second annealing procedure is selectively performed. The polysilicon layer with the anti-reflection rough surface is doped by reacting with a gas induced. Then, the thin film and the polysilicon layer with the anti-reflection rough surface is defined, whereby the poly film with an anti-reflection rough surface is formed over the substrate.

Abstract: A method for manufacturing a bit line. A substrate having a dielectric layer on the substrate and a contact hole penetrating through the dielectric layer and exposing portions of the substrate is provided. A patterned conductive layer is formed on the dielectric layer and fills the contact hole. The surface of the patterned conductive layer is converted into an oxide layer. The oxide layer is removed. A silicide layer is formed on the patterned conductive layer.

Abstract: A method for manufacturing DRAM capacitor that utilizes a self-aligned etching process for fabricating the lower electrode of a capacitor instead of a conventional photolithographic process whose processing accuracy is dependent upon the resolution of light source used. Using a polysilicon layer as a mask and a silicon nitride layer as an etching stop layer, the self-aligned etching process is carried out to form a rather narrow contact window in the insulating layer. By forming this narrow contact window, proper isolation between a word line and its neighboring conductive layer is ensured. Hence, device reliability is increased.

Abstract: The invention is a method for fabricating a capacitor in a dynamic random access memory. The capacitor has double cylinder structure and is fabricated by utilizing an insulating side wall spacer to pre-define the capacitor structure. Then, a wet etching process is applied to remove the insulating side wall spacer and expose a surface of a structured lower electrode. Then, a dielectric thin film and an upper electrode are formed over the surface of the lower electrode sequentially to form the capacitor.

Abstract: An improved method of fabricating an unlanded via hole on a semiconductor substrate is provided. A conductive line and a patterned anti-reflection coating layer are sequentially formed on the substrate wherein the patterned anti-reflection coating layer has a smaller width than the conductive line and a portion of the conductive layer is exposed by the patterned anti-reflection coating layer. A planarized dielectric layer is formed over the substrate to cover the patterned anti-reflection coating layer and the conductive line. A via hole is formed in the planarized dielectric layer to expose portions of surface and sidewalls of the patterned anti-reflection coating layer as well as the conductive line.

Abstract: A method for forming the lower electrode of a capacitor comprising the steps of forming a first dielectric layer, a silicon nitride layer and an oxide layer over a substrate. Then, a first conducting layer is formed in an opening making electrical contact with a specified region of the substrate. Next, a first hemispherical grained silicon layer and a second dielectric layer are formed over the first conductive layer. Thereafter, the second dielectric layer, the first hemispherical grained silicon layer and the first conductive layer are patterned. Subsequently, a second conductive layer and a second hemispherical grained silicon layer are formed over the whole substrate structure. Next, portions of the second hemispherical grained silicon layer and the second conductive layer lying above the oxide layer and the second dielectric layer are removed. Finally, the second dielectric layer is removed to expose the first hemispherical grained silicon layer.

Abstract: A method for fabricating a multilevel interconnect, where a first and a second conducting wires are formed respectively on a substrate, while a part of the substrate between the first and the second conducting wires is exposed. A first dielectric layer is then formed to cover the substrate as well as the first and the second conducting wires, wherein the first dielectric layer has an air gap formed between the first and the second conducting wires. An anti-etch layer is formed on the first dielectric layer above the air gap, while a second dielectric layer is then formed on the anti-etch layer and the first dielectric layer. A via opening which exposes the first conducting wire is then formed by etching, followed by forming a barrier layer which covers the profile of the via opening and the exposed surface of the first conducting layer. Consequently, a via plug is formed to fill the via opening.

Abstract: A method of forming a via is provided comprising a plasma treatment at the spin-on-glass layer after forming the unlanding via. The plasma comprises hydrogen and a second gas. The mist containing in the spin-on-glass layer is damaged and removed away.