Abstract: A method of manufacturing a flash memory structure that also includes the process of forming a shallow trench isolation structure. The method comprises the steps of providing a semiconductor substrate, and then forming a shallow trench isolation structure within the substrate. Thereafter, etching is carried out to form a shallow trench within a portion of the shallow trench isolation structure. The shallow trench is formed where a common source terminal is subsequently formed. Next, metallic material is deposited into the trench to form a buried metallic layer. Then, a stacked gate is formed above the semiconductor substrate. Finally, ions are implanted into the substrate on each side of the stacked gate using the stacked gate itself as a mask to form a source region and a drain region. The source region and the buried metallic layer are connected together to form a common source region.

Abstract: A method of fabricating bit lines by damascene. A substrate having a first dielectric layer is provided, and a bit line contact is formed within the first dielectric layer. A hard material layer is formed on the first dielectric layer to expose the bit line contact. A second dielectric layer is formed on the hard material layer. An opening and a trench are formed within the second dielectric layer to expose the bit line contact and the hard material layer. A hard material spacer is formed on the sidewall of the opening and the trench. A tungsten silicide layer fills the opening and the trench to serve as a bit line on the bit line contact and an interconnect of the bit line.

Abstract: A shallow trench isolation structure is formed by providing a pad layer and a silicon nitride polish stop layer on a surface of a P-type silicon substrate. The silicon nitride polish stop layer and the pad oxide layer are patterned to define openings corresponding to portions of the substrate that will be etched to form trenches. Trenches are defined in the P-type silicon substrate by anisotropic etching. A boron doped oxide or glass is deposited along the walls and floor of the trench. An undoped TEOS oxide is provided over the doped oxide or glass to complete filling of the trench. The device is subjected to a high temperature reflow process, causing the dielectric materials to flow, partially planarizing the device and causing the boron of the first layer to diffuse into the walls and floor of the trench. Chemical mechanical polishing removes excess portions of the dielectric layers.

Abstract: A method of removing carbon contamination. On a semiconductor substrate having carbon contamination thereon, a sacrificial oxide layer is formed. During the formation of the sacrificial oxide layer, an agent is introduced to help and improve the growth of the sacrificial oxide layer, and to trap the carbon contamination. The sacrificial oxide layer is then removed, and the carbon contamination is removed with the sacrificial oxide layer.

Abstract: A method for monitoring dosage/focus/leveling is provided. A control wafer is provided and divided into several regions. Five of the regions near the center of the wafer are used to monitor normally. Other regions are used as dummy shots. When a situation of a stepper changes greatly, the dosage/focus/leveling of the control wafer is monitored using the dummy shots. In monitoring exposure dosage, the middlemost region is monitored. One of the five regions, which is the most central, is exposed with a low exposure energy to enhance sensitivity of critical dimension versus energy. Many points with small areas are developed in the centermost region to take sufficient samples. Since the developed points are close, effects from the nonuniformity of development and from the nonuniformity of the photoresist layer are prevented. In focus/leveling monitoring, a curve diagram of exposure dosage versus critical dimension is provided. An exposure parameter is taken at a range of the curve with a large slope.

Abstract: A surface treatment method for bonding pad is described, in which a passivation layer is formed on a bonding pad and an opening is formed within the passivation by a plasma etching process. The bonding pad is corroded by the etching plasma containing fluorine during the etching process. The bonding pad is rinsed with deionized water comprising carbon dioxide to reduce the effects of the corrosion phenomenon.

Abstract: A method for manufacturing a flash memory with a shallow trench isolation and a buried bit line. In the invention, the shallow trench isolation is used as an isolation region, so that the size of the devices can be greatly reduced and the integration of the devices can be greatly increased. Additionally, the shallow trench isolation is formed in the substrate before the buried bit line implantation step is performed, so that the short channel effect caused by the lateral diffusion of the doped ions can be eliminated. Moreover, since the neighboring doped regions are electrically coupled to each other through the polysilicon layer, the access rate of the flash memory can be enhanced.

Abstract: A method for forming a DRAM capacitor comprising the steps of first depositing conductive material over a dielectric layer and into a contact opening already formed in the dielectric layer, then patterning the conductive layer using a photoresist layer. Next, a portion of the photoresist layer is removed to expose a peripheral strip on the upper surface of the conductive layer. Then, a liquid-phase deposition method is used to deposit a silicon oxide layer over the conductive layer and the dielectric layer. Due to the selectivity of liquid-phase deposition method, none of the silicon oxide layer is deposited over the photoresist layer. Hence, after the removal of the photoresist layer, the silicon oxide layer can be used as a mask for patterning the conductive layer again. The patterned conductive layer then becomes the cylindrical-shaped storage electrode of a DRAM capacitor.

Abstract: A self-aligned contact process for fabricating semiconductor devices on a semiconductor substrate is described. The present process comprises providing two gates structure on a semiconductor substrate, wherein the gate structure comprises a gate and a passivation layer on the top surface thereof. A buffer layer is conformally overlaid on the gate structure, passivation layer and the semiconductor substrate. A photoresist material is formed on the semiconductor substrate to a level between the top surface of the passivation layer and interface between the passivation layer and gate. The buffer layer is removed to the level of the photoresist layer. Next, the photoresist material is removed. A spacer is formed on the sidewall of the buffer layer and the passivation layer of the gate structure. An insulating layer is formed on the semiconductor substrate and then, a contact opening is formed therein to expose the semiconductor substrate.

Abstract: A method of forming a shallow trench isolation in a semiconductor substrate. A mask layer is formed to cover an active region of the substrate. A trench is formed within the exposed substrate. The trench is filled with an insulation layer. The dimension of the mask layer is shrunk. A thermal oxidation process is performed to form an oxide protrusion between the trench and the active region. The mask layer is removed.

Abstract: A method of fabricating a bit line on a semiconductor substrate is provided. First, an oxide layer is formed and patterned on the substrate. An epitaxial layer is formed on the exposed substrate after patterning the oxide layer. A first spacer and a second spacer are sequentially formed on the sidewalls of a opening of the oxide layer. A trench is formed by partially removing the epitaxial layer and the substrate. A liner oxide layer is formed in the trench after removing the second spacer. A polysilicon layer as a conductive layer is formed in the trench after removing the first spacer. Then, a step of ion implantation and an annealing step are carried out. A buried bit line is formed after etching back the polysilicon layer.

Abstract: A structure of a flash memory is disclosed. The flash memory includes a common drain, a memory unit which has at least one memory cell, and a depletion mode selector transistor. The depletion mode selector transistor isolates the common drain and the memory unit. Two terminals the depletion mode selector transistor are coupled to the common drain and the memory unit, respectively.

Abstract: A method for fabricating a cathode of a field emission display. A doped polysilicon layer is formed over a substrate, and the doped polysilicon layer is patterned to form a plurality of field emitters. The doped polysilicon layer and the field emitters are patterned to form a plurality of field emission arrays. Then, a sharpening process is performed to form an oxide layer on the field emitters. A first dielectric layer and a second dielectric layer are formed conformal to the substrate, and a third dielectric layer is formed on the second dielectric layer. The third dielectric layer is planarized to expose the second dielectric layer on a top portion of each of the field emitters. The exposed second dielectric layer is removed, and an oxide layer is formed on the third dielectric layer and a top surface of the first dielectric layer on the top portion of the field emitter. A self-aligned metal layer is formed on the oxide layer.

Abstract: A method is described for manufacturing shallow trench isolation. The method comprises the steps of providing a substrate having a pad oxide layer, a mask layer, a trench penetrating through the mask layer and the pad oxide and into the substrate and a first liner oxide layer in the trench. A portion of the first liner oxide layer is stripped away to expose the bottom corner of the mask layer. A portion of the mask layer is stripped away to expose the top corner of the first oxide layer. The first liner oxide layer is removed to expose the surface of the trench. A second liner oxide layer is formed on the sidewall and the base surface of the trench and the trench is filled with an insulating material to form a shallow trench isolation.

Abstract: A method for manufacturing an interconnect. A substrate having a first dielectric layer and a barrier layer formed thereon is provided. A plurality of conductive wires is formed on the barrier layer. A second dielectric layer is formed on the barrier layer exposed by the conductive wires, wherein the second dielectric layer has a surface level between the top surfaces and the bottom surfaces of the conductive wires. A spacer is formed on each portion of the sidewalls of the conductive wires exposed by the second dielectric layer, wherein there is a gap between two adjacent spacers. The second dielectric layer is removed. A third dielectric layer is formed on the conductive wires, the spacer, the sidewalls of the conductive wires and the portion of the barrier layer exposed by the conductive wires and fills the gap to form an air cavity between the conductive wires under the spacer.

Abstract: A method of fabricating a capacitor in a DRAM. A semiconductor substrate having a metal-oxide-semiconductor is provided. Using only one photolithography process, a bottom electrode is formed. By forming a dielectric layer over the substrate, and a poly-silicon layer on the dielectric layer, a capacitor is formed.

Abstract: A method for improving the differential etching rate of forming vias in a metallic layer by the addition of a nitrogen plasma processing operation into the conventional metal etching operation. The nitrogen plasma processing operation facilitates the formation of aggregates through a chemical reaction between gaseous nitrogen and metal. The aggregates are able to lower the etching rate of metal in such a way that its effect on a wide-open via is more than on a narrow-dense via. Hence, microloading effect on the etching rate is greatly improved.

Abstract: A method for manufacturing shallow trench isolation structure in a substrate, in which by forming a doped region at the upper corners of a trench, the degree of oxidation in that region increases when the liner layer is formed over the exposed surface of the trench. Therefore, thickness of the liner layer at the upper corner regions of the trench is almost the same as in other regions. Consequently, a kink effect is prevented when a gate is subsequently formed over the active region of the substrate.

Abstract: A split-gate source side injection flash memory structure that utilizes the polysilicon spacers formed on the sidewalls of the control gate and the floating gate, and the difference in concentration and depth between the source region and the drain region. By applying suitable operating voltage to the polysilicon spacers above the respective source region and drain region, operation of the flash memory can be properly controlled. Because a source-side injection is obtained in this invention, hence a higher programming efficiency is achieved.

Abstract: A method of fabricating a dual damascene structure. A low k dielectric layer and a cap layer are successively formed on a substrate having an active region. A first photoresist layer is formed on the cap layer and the cap layer is then patterned to expose a portion of the low k dielectric layer. The first photoresist layer and a portion of the low k dielectric layer are simultaneously removed to form a wiring line opening. A second photoresist layer is formed on the cap layer to cover a portion of the wiring line opening. When the step of removing the second photoresist layer is performed, a via hole is formed to expose the active region by simultaneously removing the exposed low k dielectric layer. The via hole and the wiring line opening are filled with a metal layer to form a wiring line and a via.