Abstract: A method of fabricating a flash memory. After the formation of a trench isolation structure, openings are formed, in a direction perpendicular to the orientation of the trench isolation structure, in order to form a buried bit line. A spacer is formed on the opening sidewall of the bit line in which the distance between a top of the spacer and the interface of a substrate and a pad oxide layer is the depth of the source/drain region. The opening is then filled with a doped polysilicon conducting layer used as the buried bit line. The dopant from the polysilicon conducting layer is driven into the substrate to form the source/drain region.

Abstract: A method for fabricating a flash memory is provided. The method contains sequentially forming a tunneling oxide layer, a polysilicon layer, and a silicon nitride layer on a semiconductor substrate. Patterning the silicon nitride layer, polysilicon layer, the tunneling oxide layer, and the substrate forms a trench in the substrate. A shallow trench isolation (STI) structure is formed to fill the trench up the silicon nitride layer. The silicon nitride layer is removed to expose the polysilicon layer and a portion of each sidewall of the STI structure. A polysilicon spacer is formed on each exposed sidewall of the STI structure. An upper portion of the STI structure is removed so as to expose a portion of each sidewall of the polysilicon layer. The polysilicon layer serves as a floating gate. A conformal dielectric layer and a top polysilicon layer are formed over the substrate.

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor on a semiconductor substrate is described. The invention introduces an air chamber with a low dielectric constant between the gate and the source/drain region so as to lower the fringing electric field between the gate and the source/drain region. Moreover, the dielectric constant of the dielectric layer between the gate and the source/drain region is reduced. Therefore, the gate-to-drain capacitance is decreased in the MOS transistor.

Abstract: The invention relates to a method for manufacturing of a titanium self-aligned silicide (Salicide). This process includes of forming a metal layer over the surfaces of the semiconductor substrate and the gate electrode. Then, a rapid thermal process is performed with three stages to form the salicide, for example, titanium silicide, at the interface between the titanium and silicon, namely on the surfaces of the gate electrode and source/drain region. The rapid thermal process with three stages includes using the first stage with the first temperature to form the early titanium silicide having the C49 phase. The temperature is raised to a second temperature and the RTA process is performed with nitrogen gases to transform the high resistance phase C49 of the titanium nitride into a low resistance phase C54 in the second stage. Then, the temperature is rapidly raised to a third temperature to transform the C49 phase into the C54 phase completely and to prevent the agglomeration phenomenon.

Abstract: A Method for forming a dynamic random access memory device with an ultra-short channel and an ultra-shallow junction is described in the invention. In the invention, the spacer is used as a mask to define the channel length of the device, so that the channel length of the device is not limited by the resolution of the photolithography process, and the performance of the device is improved thereby. Furthermore, an inversion layer serves as a junction to reduce the electric field; thus, the reliability of the device is increased.

Abstract: An improved method for oxide etching that uses of a mixture of etching gases including CF.sub.4 /C.sub.4 F.sub.8 /CO/Ar/N.sub.2 such that etching selectivity between oxide and other materials can be increased. Furthermore, the addition of a cleaning step between etching operations in this invention is able to remove most of the deposited polymers formed during the etching operation, hence etching stop phenomenon can be prevented. Also, the presence of N.sub.2 in the etching gas mixture is able to prevent the formation of polymers on the sidewalls of an etched contact opening. Hence, when metal is subsequently deposited into the opening to form a self-aligned silicide layer, there are few polymers to react with the metal atoms to form a layer of high resistance material on the sidewalls of the opening. Thus, reliability of the device can be maintained.

Abstract: A method for manufacturing a dual-cylinder bottom electrode. Because the node contact hole is formed by self-aligned etching and the materials of the spacers are conductive materials, the node contact hole is smaller than the resolution of the photolithography. Hence, the size of the device can be greatly reduced. Furthermore, because of the dual-cylinder bottom electrode, the surface area of the bottom electrode is enlarged in a limited space. Therefore, the capacitance of the capacitor is increased.

Abstract: A method for forming a via hole provides a substrate, and a conducting layer is formed on the substrate. An intermetal dielectric layer is deposited conformal to the substrate, and a patterned photoresist is formed on the intermetal dielectric layer. The photoresist is used as a mask, and a portion of intermetal dielectric layer, which is not covered by the photoresist, is removed to expose the conducting layer, so that an opening is formed. A polymer layer is unavoidably formed on the surface of the opening, and then the photoresist and the polymer layer are removed. The residual polymer layer is removed by wet bench to form a via hole.

Abstract: A method of forming the gate terminal of a device. The method includes forming spacers on top of the gate polysilicon layer and near the side edges thereof, and then etching the gate polysilicon layer to form a groove using the spacers as a mask. Hence, the exposed surface area of the gate polysilicon layer is increased. Finally, a metal silicide layer is formed over the gate polysilicon layer, producing a low resistance gate.

Abstract: A three-dimensional flash array structure and the fabrication method thereof. The three-dimensional flash memory array structure disclosed in the invention can be expanded volumetrically, so that a memory cell with large capacity can be manufactured in a unit area to increase the memory capacity.

Abstract: A method of fabricating a capacitor. A transistor is formed on a substrate. The transistor comprises a gate and a source/drain region. A dielectric layer is formed over the substrate. A covering layer is formed on the dielectric layer. Portions of the covering layer and the dielectric layer are removed to form a contact opening. The contact opening exposes a portion of the source/drain region. A polysilicon layer is formed over the substrate to fill the contact opening. The polysilicon layer is electrically coupled with the source/drain region. A patterned photoresist layer is formed on the polysilicon layer above the contact opening. An anisotropic etching step is performed with the photoresist layer serving as a mask until a portion of the covering layer is exposed. An oxide layer is formed on the exposed covering layer. The surface of the oxide layer is higher than the surface of the polysilicon layer. The photoresist layer is removed to expose a portion of a sidewall of the polysilicon layer.

Abstract: A method of forming a test key architecture on a silicon wafer. The method includes forming trench isolation regions between a source region and a drain region. Thereafter, a plurality of active regions are formed in parallel above the trench isolation regions such that the smallest possible width for each active region is chosen to reduce overall area occupation and increase the number of test keys. Next, a long pass gate is formed above the trench isolation regions, crossing and covering the parallel-connected active regions. Consequently, the effect due to stress-induced defect and the probability of leakage current due to parasitic device effect are greatly increased.

Abstract: The invention provides a method of manufacturing a metal interconnect. A substrate having a metal line formed thereon is provided. An anti-reflection layer is formed on the metal line. A dielectric layer with a relatively low dielectric constant is formed over the substrate. A patterned photoresist layer is formed on the dielectric layer. The patterned photoresist layer has an opening exposing a portion of the dielectric layer. The portion of the dielectric layer exposed by the opening is removed to form a via hole. The patterned photoresist layer is removed by an O.sub.2 --H.sub.2 O--CF.sub.4 plasma. The pressure of the O.sub.2 --H.sub.2 O--CF.sub.4 plasma is about 800-1000 torr. A cleaning process is performed by a post-stripper rinse solution and de-ionized water without using an acetone solution. A barrier layer is formed over the substrate by chemical vapor deposition. A metal nucleation is performed for a long time by chemical vapor deposition to form metal nuclei on the barrier layer.

Abstract: A method for fabricating a STI structure includes a pad oxide layer and a hard masking layer are sequentially formed over a semiconductor substrate. A trench is formed in the substrate by patterning over the substrate. A liner oxide layer is formed over a side-wall of the trench in the substrate. An isolating layer by APCVD and an isolating layer by HDPCVD are sequentially formed over the substrate, in which the height of the CVD isolating layer within the trench is lower than the height of the hard masking layer. A CMP process is performed, using the hard masking layer as a polishing stop. The hard masking layer and the pad oxide layer are removed to accomplish the STI structure.

Abstract: A method for fabricating a transistor with a borderless contact is provided. The method contains forming several dummy gates on a substrate. Each dummy gate includes a pad oxide layer and a dummy gate layer. A doped polysilicon layer is formed on the substrate at each side of the dummy gates. A shallow trench isolation (STI) is formed to define active regions. A horizontal gate opening is formed to expose two adjacent dummy gates. The dummy gate layer is removed to expose sidewalls of the doped polysilicon. Spacers are formed on the exposed sidewalls of the doped polysilicon layer. A threshold voltage doped region and an anti-punch-through doped region are formed in the substrate by ion implantation, using the doped polysilicon layer and the spacers as a mask. The exposed pas oxide layer is removed and a gate oxide layer is formed instead. A gate metal layer is formed on the gate oxide layer between the spacers, in which the horizontal gate opening is also filled.

Abstract: A fluid delivering system receives a fluid from a supplying device, transfers the fluid to an operational device and then dumps the used fluid into an extraction device. The fluid delivering system has a main pipeline system and at least a secondary pipeline system. Each pipeline system uses a first flow valve to control the back flow of fluid to a first flow controller, a second flow valve to protect a pressure gauge and a third flow valve to control the flow of fluid to a pressure controller. Through the relative positioning and the concerted actions of these three valves, any malfunctioning in the fluid delivering system can be detected quickly so that on-going processing operation can stop immediately to minimize product damages.

Abstract: The present invention provides a method of fabricating a flash memory cell without silicide formation on the source regions. A liquid deposition oxide layer is formed selectively only on a common source region by using a mask layer. The liquid deposition oxide layer is formed on the common source region in order to cover the common source region. Therefore, once a salicide step is performed, a silicide layer will not form on the common source region.

Abstract: A method for fabricating a passivation layer. An isolation layer is formed on a metal layer over the substrate. The isolation layer on the metal layer is removed by chemical-mechanical polishing and dry etching. The planarization of the metal layer thus is obtained. A passivation layer having a certain structure and a thickness combination of different layers is formed over the substrate. The reflection rate of the metal layer is significantly enhanced.

Abstract: A method of optical proximity correction. A main pattern is provided. The main pattern has a critical dimension. When the critical dimension is reduced to reach a first reference value or below, a serif/hammerhead is added onto the main pattern. When the critical dimension is further reduced to a second reference value or below, an assist feature is added onto the main pattern. The corrected pattern is then transferred to a layer on wafer with an improved fidelity.

Abstract: A method of forming a layer of hemispherical grain polysilicon over the lower electrode of a capacitor. The method comprises the steps of providing a substrate that has a field effect transistor already formed thereon, and then forming an insulating layer with a contact opening over the substrate. Subsequently, a polysilicon layer is formed over the insulating layer that completely fills the contact opening. This polysilicon layer is electrically coupled to one of the source/drain regions of the field effect transistor. Thereafter, a thin buffer layer is formed over the polysilicon layer, and then the thin buffer layer is patterned. The thin buffer layer is used as a mask for covering the polysilicon layer that is to be part of the lower electrode of a capacitor. Next, a plasma etching operation is carried out to remove the thin buffer layer and a portion of the polysilicon layer at the same time.