Abstract: A Programmable Logic Device (PLD) structure using third dimensional memory is disclosed. The PLD structure includes a switch configured to couple a polarity of a signal (e.g., an input signal applied to an input) to a routing line and a non-volatile register configured to control the switch. The non-volatile register may include a non-volatile memory element, such as a third dimension memory element. The non-volatile memory element may be a two-terminal memory element that retains stored data in the absence of power and stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage across the two terminals. Logic and other active circuitry can be positioned in a substrate and the non-volatile memory element can be positioned on top of the substrate.

Abstract: A threshold device including a plurality of adjacent tunnel barrier layers that are in contact with one another and are made from a plurality of different dielectric materials is disclosed. A memory plug having first and second terminals includes, electrically in series with the first and second terminals, the threshold device and a memory element that stores data as a plurality of conductivity profiles. The threshold device is operative to impart a characteristic I-V curve that defines current flow through the memory element as a function of applied voltage across the terminals during data operations. The threshold device substantially reduces or eliminates current flow through half-selected or un-selected memory plugs and allows a sufficient magnitude of current to flow through memory plugs that are selected for read and write operations. The threshold device reduces or eliminates data disturb in half-selected memory plugs and increases S/N ratio during read operations.

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract: A memory using a tunnel barrier that has a variable effective width is disclosed. A memory element includes a tunneling barrier and a conductive material. The conductive material typically has mobile ions that either move towards or away from the tunneling barrier in response to a voltage across the memory element. A low conductivity region is either formed or destroyed. It can be formed by either the depletion or excess ions around the tunneling barrier, or by the mobile ions combining with complementary ions. It may be destroyed by either reversing the forming process or by reducing the tunneling barrier and injecting ions into the conductive material. The low conductivity region increases the effective width of the tunnel barrier, making electrons tunnel a greater distance, which reduces the memory element's conductivity. By varying conductivity multiple states can be created in the memory cell.

Abstract: Circuitry for restoring data values in re-writable non-volatile memory is disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory elements. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory elements substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory elements may have a value of the stored data restored (e.g., re-written to the same cell or another cell) if the value is not associated with a read margin (e.g., a hard programmed or hard erased state).

Abstract: A non-volatile register is disclosed. The non-volatile register includes a memory element. The memory element comprises a first end and a second end. The non-volatile register includes a register logic connected with the first and second ends of the memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.

Abstract: Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for accessing memory in multiple layers of memory implementing, for example, third dimension memory technology. In a specific embodiment, an integrated circuit is configured to implement write buffers to access multiple layers of memory. For example, the integrated circuit can include memory cells disposed in multiple layers of memory. In one embodiment, the memory cells can be third dimension memory cells. The integrated circuit can also include read buffers that can be sized differently than the write buffers. In at least one embodiment, write buffers can be sized as a function of a write cycle. Each layer of memory can include a plurality of two-terminal memory elements that retain stored data in the absence of power and store data as a plurality of conductivity profiles.

Abstract: Circuits to control access to memory; for example, third dimension memory are disclosed. An integrated circuit (IC) may be configured to control access to memory cells. For example, the IC may include a memory having memory cells that are vertically disposed in multiple layers of memory. The IC may include a memory access circuit configured to control access to a first subset of the memory cells in response to access control data in a second subset of the memory cells. Each memory cell may include a non-volatile two-terminal memory element that stores data as a plurality of conductivity profiles that can be non-destructively sensed by applying a read voltage across the two terminals of the memory element. New data can be written by applying a write voltage across the two terminals of the memory element. The two-terminal memory elements can be arranged in a two-terminal cross-point array configuration.

Abstract: A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e.g., electrical current) and does not require electrodes (e.g., anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 ?. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e.g., catalytic converters), and irregularly shaped metal surfaces.

Abstract: Chemical mechanical polishing (CMP) of thin film materials using a slurry including a surfactant chemical operative to polish high portions of the film being planarized while preventing the polishing of low portions of the film is disclosed. The low portions can be in a step reduction region of a deposited film. The CMP process can be used for form a planar surface upon which subsequent thin-film layers can be deposited, such as an electrically conductive material for an electrode. The subsequently deposited thin-film layers are substantially planar as deposited without having to use CMP. The resulting thin-film layers are planar and have a uniform cross-sectional thickness that can be beneficial for layers of memory material for a memory cell. The processing can be performed back-end-of-the-line (BEOL) on a previously front-end-of-the-line (FEOL) processed substrate (e.g., silicon wafer) and the BEOL process can be used to fabricate two-terminal non-volatile cross-point memory arrays.

Abstract: Embodiments relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement a memory architecture that includes local bit lines for accessing subsets of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point memory array formed above a logic layer. The cross-point memory array includes X-lines and Y-lines, of which at least one Y-line includes groups of Y-line portions. Each of the Y-line portions can be arranged in parallel with other Y-line portions within a group of the Y-line portions. Also included are memory elements disposed between a subset of the X-lines and the group of the Y-line portions. In some embodiments, a decoder is configured to select a Y-line portion from the group of Y-line portions to access a subset of the memory elements.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to generate access signals to facilitate memory operations in scaled arrays of memory elements, such as memory implemented in third dimensional memory technology formed BEOL directly on top of a FEOL substrate that includes data access circuitry. In at least some embodiments, a non-volatile memory device can include a cross-point array having resistive memory elements disposed among word lines and subsets of bit lines, and an access signal generator. The access signal generator can be configured to modify a magnitude of a signal to generate a modified magnitude for the signal to access a resistive memory element associated with a word line and a subset of bit lines. The modified magnitude can be a function of the position of the resistive memory element in the cross-point array.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations that affect the operation of memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes a cross-point array comprising memory elements disposed among word lines and bit lines, where a parameter can affect the operating characteristics of a memory element. The integrated circuit further includes a data signal adjuster configured to modify the operating characteristic to compensate for a deviation from a target value for the operating characteristic based on the parameter. In some embodiments, the memory element, such as a resistive memory element, is configured to generate a data signal having a magnitude substantially at the target value independent of variation in the parameter.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement memory architectures configured to enhance throughput for cross point arrays including memory elements, such as memory elements based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes arrays that include memory elements being formed BEOL above a FEOL logic layer within a boundary in a plane parallel to a substrate, and array lines. Further, the integrated circuit includes array line decoders disposed in the logic layer within a region located coextensive with the boundary and between the substrate and the arrays. In some embodiments, the disposition of peripheral circuitry, such as the array line decoders, under the arrays can preserve or optimize die efficiency for throughput enhancement.

Abstract: A memory cell including conductive oxide electrodes is disclosed. The memory cell includes a memory element operative to store data as a plurality of resistive states. The memory element includes a layer of a conductive metal oxide (CMO) (e.g., a perovskite) in contact with an electrode that may comprise one or more layers of material. At least one of those layers of material can be a conductive oxide (e.g., a perovskite such as LaSrCoO3-LSCoO or LaNiO3-LNO) that is in contact with the CMO. The conductive oxide layer can be selected as a seed layer operative to provide a good lattice match with and/or a lower crystallization temperature for the CMO. The conductive oxide layer may also be in contact with a metal layer (e.g., Pt). The memory cell additionally exhibits non-linear IV characteristics, which can be favorable in certain arrays, such as non-volatile two-terminal cross-point memory arrays.

Abstract: Embodiments of the invention relate generally to semiconductors and memory technology, and more particularly, to systems, integrated circuits, and methods to implement circuits configured to compensate for parameter variations in layers of memory by adjusting access signals during memory operations. In some embodiments, memory cells are based on third dimensional memory technology. In at least some embodiments, an integrated circuit includes multiple layers of memory, a layer including sub-layers of semiconductor material. The integrated circuit also includes an access signal generator configured to generate an access signal to facilitate an access operation, and a characteristic adjuster configured to adjust the access signal for each layer in the multiple layers of memory.

Abstract: Circuitry and methods for restoring data in memory are disclosed. The memory may include at least one layer of a non-volatile two-terminal cross-point array that includes a plurality of two-terminal memory elements that store data as a plurality of conductivity profiles and retain stored data in the absence of power. Over a period of time, logic values indicative of the stored data may drift such that if the logic values are not restored, the stored data may become corrupted. At least a portion of each memory may have data rewritten or restored by circuitry electrically coupled with the memory. Other circuitry may be used to determine a schedule for performing restore operations to the memory and the restore operations may be triggered by an internal or an external signal or event. The circuitry may be positioned in a logic layer and the memory may be fabricated over the logic layer.

Abstract: A system and a method for emulating a NAND memory system are disclosed. In the method, a command associated with a NAND memory is received. After receipt of the command, a vertically configured non-volatile memory array is accessed based on the command. In the system, a vertically configured non-volatile memory array is connected with an input/output controller and a memory controller. The memory controller is also connected with the input/output controller. The memory controller is operative to interface with a command associated with a NAND memory and based on the command, to access the vertically configured non-volatile memory array for a data operation, such as a read operation or write operation. An erase operation on the vertically configured non-volatile memory array is not required prior to the write operation. The vertically configured non-volatile memory array can be partitioned into planes, blocks, and sub-planes, for example.

Abstract: The various embodiments of the invention relate generally to semiconductors and memory technology. More specifically, the various embodiment and examples of the invention relate to memory devices, systems, and methods that protect data stored in one or more memory devices from unauthorized access. The memory device may include third dimension memory that is positioned on top of a logic layer that includes active circuitry in communication with the third dimension memory. The third dimension memory may include multiple layers of memory that are vertically stacked upon each other. Each layer of memory may include a plurality of two-terminal memory elements and the two-terminal memory elements can be arranged in a two-terminal cross-point array configuration. At least a portion of one or more of the multiple layers of memory may include an obfuscation layer configured to conceal data stored in one or more of the multiple layers of memory.

Abstract: Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals.