Patents Assigned to University of Electronic Science and Technology
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Patent number: 8941207Abstract: A method or an auxiliary method to implement Optimum Variation Lateral Electric Displacement uses an insulator film(s) containing conductive particles covering on the semiconductor surface. This film(s) is capable of transmitting electric displacement into or extracting it from the semiconductor surface, or even capable of extracting some electric displacement from a part of the semiconductor surface and then transmitting it to another part of the surface. Optimum Variation Lateral Electric Displacement can be used to fabricate lateral high voltage devices, or as the edge termination for vertical high voltage devices, or to make capacitance. It can be further used to prevent strong field at the boundaries of semiconductor regions of different types of conductivity types.Type: GrantFiled: January 11, 2013Date of Patent: January 27, 2015Assignee: University of Electronic Science and TechnologyInventor: Xingbi Chen
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Patent number: 8907650Abstract: This invention involves a bandgap reference circuit in IC. The temperature coefficient of conventional bandgap reference is large and the higher order compensation is difficult to implement. This invention provides an adaptive compensated bandgap reference which solves the problem only using lower order (first order) temperature coefficient compensation. The invention adopts segmental compensation circuit to realize adaptive segmental compensation of bandgap reference with low temperature coefficient. The technical solution includes traditional bandgap voltage reference circuit and adaptive feedback compensation circuit which consists of sample and hold circuit, voltage comparator and control module. This invention controls the bandgap voltage reference through systematical view and it has high process compatibility.Type: GrantFiled: February 28, 2011Date of Patent: December 9, 2014Assignee: University of Electronic Science and Technology of ChinaInventors: Shaowei Zhen, Ping Luo, Ruhui Yang, Kang Yang, Bo Zhang
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Patent number: 8890280Abstract: The present invention relates to a semiconductor device. The device comprises a semiconductor substrate. A semiconductor drift region is on the semiconductor substrate. The semiconductor drift region comprises a semiconductor region of a first conduction type and a semiconductor region of a second conduction type. The semiconductor region of the first conduction type and the semiconductor region of the second conduction type form a superjunction structure. A high-K dielectric is on the semiconductor substrate. The high-K dielectric is adjacent to the semiconductor region of the second conduction type. An active region is on the semiconductor drift region. A trench gate structure is on the high-K dielectric, the trench gate structure being adjacent to the active region. The semiconductor region of the second conduction type is formed by shallow angle ion implantation, thus its width is narrow and its concentration is high.Type: GrantFiled: February 24, 2011Date of Patent: November 18, 2014Assignee: University of Electronic Science and Technology of ChinaInventors: Xiaorong Luo, Guoliang Yao, Tianfei Lei, Yuangang Wang, Bo Zhang
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Publication number: 20140316728Abstract: The present invention provides a SOC estimation method applied to a battery system comprising a battery pack. The SOC estimation method comprises the steps of: determining an initial SOC value; determining whether the battery pack is in a working status; measuring the voltage and current of the battery pack if the battery pack is in the working status; calculating a current SOC value by using an ampere-hour method based on the initial SOC value and the measured voltage and current; determining dynamic characteristic parameters of the battery pack; and optimizing the current SOC value by using extended Kalman filter (EKF) method and based on the dynamic characteristic parameters of the battery pack.Type: ApplicationFiled: February 27, 2014Publication date: October 23, 2014Applicant: University of Electronic Science and Technology of ChinaInventors: Qishui Zhong, Baihua Li, Hui Li, Yuqing Zhao
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Patent number: 8866462Abstract: This invention involves with a low power IC (Integrated Circuit) with high energy efficiency. This invention describes a Buck converter that can track the minimum energy point of the load. It works by estimating input energy of every sensing period, taking advantage of energy consumption curve of IC in sub-threshold. Energy estimation is implemented with counting conducted pulses, while maintaining constant input energy of each pulse by regulating output voltage and ON time with digital control circuit. With digital control circuit, minimum energy point can be tracked with a lookup table stored inside. Most of this invention's control circuit is digital, with benefits of low power consumption and small chip area.Type: GrantFiled: February 28, 2011Date of Patent: October 21, 2014Assignee: University of Electronic Science and Technology of ChinaInventors: Ping Luo, Shaowei Zhen, Xiang Geng, Ye Zhang, Yajuan He, Bo Zhang
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Patent number: 8837551Abstract: A method for generating high power electromagnetic radiation based on double-negative metamaterial (DNM), includes providing electrons of an electron beam moving in a vacuum close to an interface between the DNM and the vacuum at a predetermined average speed larger than a phase velocity of an electromagnetic wave propagating in the DNM so as to generate coherent high power radiation. The method can be applied but not limited to high power and compact Terahertz radiation sources and Cherenkov particle detectors and emitters.Type: GrantFiled: August 20, 2012Date of Patent: September 16, 2014Assignee: University of Electronic Science and Technology of ChinaInventors: Zhaoyun Duan, Xin Guo, Chen Guo, Yubin Gong, Min Chen
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Patent number: 8823262Abstract: The present invention provides a helical slow-wave structure, including a helix, a metal barrel and several supporting rods. The plurality of supporting rods may be inserted into the lines of the grooves tightly, this increases the contact area between the helix and the plurality of supporting rods. With a proper assembly method, the thermal contact resistance between helix and supporting rod may be decreased. So, the invention may enhance the capability of transferring the heat out of the helical slow-wave structure. The helix may have higher heat capacity, therefore, the helical slow-wave structure may become more firm, and more reliable.Type: GrantFiled: January 6, 2012Date of Patent: September 2, 2014Assignee: University of Electronic Science and Technology of ChinaInventors: Yanyu Wei, Luwei Liu, Yubin Gong, Xiong Xu, Hairong Yin, Lingna Yue, Yang Liu, Jin Xu, Wenxiang Wang
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Publication number: 20140188419Abstract: The present invention provides a method for measuring the waveform capture rate of parallel digital storage oscilloscope. On the basis of double pulse measurement, and in consideration of the asymmetry of acquisition and the refreshing time of parallel DSO, the present invention provides a step amplitude-frequency combined pulse measurement to measure the time for waveform acquisition and mapping Tmap, the number of captured waveforms before LCD refreshing Wacq and the dead time caused by LCD refreshing TDDT, and then calculates the actual measured average WCR of parallel DSO, according to the measured data, so that the WCR of parallel can be measured.Type: ApplicationFiled: October 18, 2013Publication date: July 3, 2014Applicant: University of Electronic Science and Technology of ChinaInventors: Hao ZENG, Peng YE, Kuojun YANG, Guang YANG, Qinchuan ZHANG
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Publication number: 20140183360Abstract: A long-distance polarization and phase-sensitive reflectometry based on random laser amplification for extending a sensing distance includes a long-distance polarization and phase-sensitive reflectometry of a distributed Raman amplification based on optical fiber random lasers generated by unilateral pumps, a long-distance polarization and phase-sensitive reflectometry of a distributed Raman amplification based on optical fiber random lasers generated by bilateral pumps, and a long-distance polarization and phase-sensitive reflectometry of a Raman amplification based on a combination of optical fiber random lasers generated by unilateral pumps and a common Raman pump source, which are applied in optical fiber perturbation sensing and have a capability of greatly improving a working distance of a sensing system and a high practicability.Type: ApplicationFiled: March 9, 2014Publication date: July 3, 2014Applicant: University of Electronic Science and Technology of ChinaInventors: Yunjiang Rao, Zinan Wang, Zengling Ran
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Patent number: 8734011Abstract: The present invention discloses distributed optical fiber temperature sensor based on optical fiber delay technology, including a tunable optical transmitter module, an optical receiver module, a signal processing and controlling module and multiple distributed sensing modules connected in series via transmission fibers. The multiple wavelengths optical signals transmitted from the tunable optical transmitter module respectively are transmitted into the first sensing module, and then transmitted out from the last sensing module. The output multiple wavelengths optical signals arrive at the optical receiver module. The optical receiver module converts optical signals of all wavelengths into electrical signals and transmits them into the signal processing and controlling module.Type: GrantFiled: May 6, 2012Date of Patent: May 27, 2014Assignee: University of Electronic Science and Technology of ChinaInventors: Qi Qiu, Jun Su, Shuangjin Shi, Yun Liao, Caidong Xiong
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Patent number: 8716794Abstract: The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration.Type: GrantFiled: August 10, 2010Date of Patent: May 6, 2014Assignee: University of Electronic Science and Technology of ChinaInventors: Xiaorong Luo, Florin Udrea
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Publication number: 20140118726Abstract: A device for measuring refractive index of medium based on optical delay technology comprises: a signal processing and controlling module, an optical transmitter module, and an optical receiver module, wherein the signal processing and controlling module controls the optical transmitter module to transmit an optical signal having a certain wavelength; the optical signal is injected into a medium to be measured; the optical signal is transmitted and delayed by the medium; the optical receiver module receives the optical signal delayed, and transforms the optical signal delayed into a electrical signal; the electrical signal is amplified and transmitted to the signal processing and controlling module; the signal processing and controlling module measures a delay time between transmitting and receiving the optical signal; and the refractive index of the medium at the certain wavelength is calculated based on the delay time and a known length of the medium.Type: ApplicationFiled: October 30, 2013Publication date: May 1, 2014Applicant: University of Electronic Science and Technology of ChinaInventor: Qi Qiu
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Patent number: 8704329Abstract: SOI devices for plasma display panel driver chip, include a substrate, a buried oxide layer and an n-type SOI layer in a bottom-up order, where the SOI layer is integrated with an HV-NMOS device, an HV-PMOS device, a Field-PMOS device, an LIGBT device, a CMOS device, an NPN device, a PNP device and an HV-PNP device; the SOI layer includes an n+ doped region within the SOI layer at an interface between the n-type SOI layer and the buried oxide layer; and the n+ doped region has a higher doping concentration than the n-type SOI layer.Type: GrantFiled: December 29, 2010Date of Patent: April 22, 2014Assignee: University of Electronic Science and Technology of ChinaInventors: Ming Qiao, Bo Luo, Xi Hu, Jun Ye, Bo Zhang, Zhaoji Li
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Patent number: 8648887Abstract: A method for adjusting the waveform brightness for a waveform formatted to be displayed on a digital three-dimensional (3D) oscilloscope having M brightness gradation levels to display the waveform on a digital 3D oscilloscope having L brightness gradation levels is includes, creating a ROM in an FPGA and storing a look-up table of screen display brightness value of LCD that is corresponding to the waveform occurrence N(T,A) at the current brightness gradation L. The ROM is divided into 2a sub ROMs, each sub ROM has the capacity of 2b×d bits. A value of round(pL·N(T,A) is assigned to waveform brightness value D(T,A) and is stored correspondingly into the subROML of 2b×d bits by ascending order of the b bits of binary data of waveform occurrence N(T,A). In this way, using the b bits of binary data of waveform occurrence N(T,A) as the binary address of the subROML, corresponding waveform brightness value D(T,A) at the current brightness gradation L can be obtained through look-up table in the subROML.Type: GrantFiled: September 26, 2011Date of Patent: February 11, 2014Assignee: University of Electronic Science and Technology of ChinaInventors: Shulin Tian, Peng Ye, Lianping Guo, Jun Jiang, Duyu Qiu, Qinchuan Zhang, Hao Zeng, Chuanyun Xiang, Kuojun Yang
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Publication number: 20130335045Abstract: This invention relates to the output voltage regulator of step-down switching power converters. This invention provides regulator with digitally adjusted output voltage. It solves the problem of low regulation due to low error amplifier (EA) gain. This invention is a power converter with the function of Digitally Error Correction, consisting of Logic Control, EA, PWM comparator, Driver, power devices and passive components. It features Digital Calibration Circuit whose input terminal is connected to the output voltage and output terminal is connected to the error signal. When the output voltage exceeds the tolerance range, this Digital Calibration Circuit will increase or decrease the error signal step by step, keeping the output voltage in the tolerance range. The Digital Calibration Circuit of this invention can be applied not only in nanometer scale process, but also in traditional process. For those power converters in traditional process, it is also quite promising in applications.Type: ApplicationFiled: March 17, 2011Publication date: December 19, 2013Applicant: University of Electronic Science and Technology of ChinaInventors: Bo Zhang, Shaowei Zhen, Ping Luo, Xiaohui Zhu, Jiangkun Li
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Patent number: 8598658Abstract: A high voltage lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) comprises a substrate; an epitaxy layer on the substrate; a drift region on the epitaxy layer; and a drain region and a source region at two ends. At least one pair of n-type and p-type semiconductor regions is arranged alternately above the interface of the substrate and the epitaxy layer and firmly attached to a lower surface of the drifting region; the n-type and p-type semiconductor regions are firmly closed to each other and arranged to form a lateral PN junction; and the p-type semiconductor region and the drifting region form a vertical PN junction. The n-type and p-type semiconductor regions are also totally called “a reduced surface field (RESURF) layer in body”, and the LDMOS device with a RESURF layer in body effectively solves conflict between raising reverse withstand voltage and reducing forward on-resistance of the current LDMOS devices.Type: GrantFiled: April 28, 2011Date of Patent: December 3, 2013Assignee: University of Electronic Science and Technology of ChinaInventors: Jian Fang, Lvyun Chen, Wenchang Li, Chao Guan, Qiongle Wu, Wenbin Bo, Zehua Wang
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Patent number: 8588611Abstract: The present invention provides a method for establishing an inter-domain path that satisfies wavelength continuity constraint. The fPCE stores a virtual topology comprised by border nodes of all domains. The present invention uses parallel inter-domain path establishment method to decrease the influence from WCC. Compared with the sequential process way in prior art, it enhanced the resource utilization and decreased computation delay.Type: GrantFiled: September 6, 2011Date of Patent: November 19, 2013Assignee: University of Electronic Science and Technology of ChinaInventors: Keping Long, Yunfeng Peng, Zongwei Wang, Zhen Chen, Yin Wang
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Publication number: 20130214355Abstract: A high voltage lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) comprises a substrate; an epitaxy layer on the substrate; a drift region on the epitaxy layer; and a drain region and a source region at two ends. At least one pair of n-type and p-type semiconductor regions is arranged alternately above the interface of the substrate and the epitaxy layer and firmly attached to a lower surface of the drifting region; the n-type and p-type semiconductor regions are firmly closed to each other and arranged to form a lateral PN junction; and the p-type semiconductor region and the drifting region form a vertical PN junction. The n-type and p-type semiconductor regions are also totally called “a reduced surface field (RESURF) layer in body”, and the LDMOS device with a RESURF layer in body effectively solves conflict between raising reverse withstand voltage and reducing forward on-resistance of the current LDMOS devices.Type: ApplicationFiled: April 28, 2011Publication date: August 22, 2013Applicant: University of Electronic Science and Technology of ChinaInventors: Jian Fang, Lvyun Chen, Wenchang Li, Chao Guan, Qiongle Wu, Wenbin Bo, Zehua Wang
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Publication number: 20130193509Abstract: The present invention relates to a semiconductor power device and power integrated circuits (ICs). The lateral SOI MOSFET in the present comprises a trench gate extended to the dielectric buried layer, one or multiple dielectric trenches in the drift region, and a buried gate in said dielectric trench. The permittivity of the dielectric in said dielectric trench is lower than that of said active layer. Firstly, said dielectric trench not only greatly improves breakdown voltage, but also reduces pitch size. Secondly, the trench gate widens the effective conductive region in the vertical direction. Thirdly, dual gates of said trench gate and buried gate increase channel and current densities. Thereby, specific on-resistance and the power loss are reduced. The device of the present invention has many advantages, such as high voltage, high speed, low power loss, low cost and ease of integration.Type: ApplicationFiled: August 10, 2010Publication date: August 1, 2013Applicant: University of Electronic Science and Technology of ChinaInventors: Xiaorong Luo, Florin Udrea
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Patent number: 8489916Abstract: A multi-disk fault-tolerant system, a method for generating a check block, and a method for recovering a data block are provided. The multi-disk fault-tolerant system includes a disk array and a calculation module connected through a system bus, the disk array is formed by p disks, and a fault-tolerant disk amount of the disk array is q; data in the disk array is arranged according to a form of a matrix M of (m+q)×p, where m is a prime number smaller than or equal to p?q; in the matrix M, a 0th row is virtual data blocks being virtual and having values being 0, a 1st row to an (m?1)th row are data blocks, an mth row to an (m+q?1)th row are check blocks. Therefore, during a procedure of generating the check block and recovering the data block in the multi-disk fault-tolerant system, calculation complexity is lowered.Type: GrantFiled: February 3, 2012Date of Patent: July 16, 2013Assignees: Chengdu Huawei Symantec Technologies Co., Ltd., University of Electronic Science and Technology of ChinaInventors: Yulin Wang, Jianye Yao