Patents Assigned to University of Electronic Science and Technology
  • Patent number: 10386391
    Abstract: The invention discloses a monitoring system for estimation of phase conductor parameters of overhead high voltage transmission lines. Particularly, these parameters include electric current, conductor clearance from ground and wind induced conductor motion. This is realized by utilizing magnetic field sensing at various points or of various components with state of art Tunnel Magneto resistive sensors. The measured data is then divided into two groups, where one group performs the reconstruction using magnetic field and the other group validates the reconstructed results. For each group, initial conductor to sensor position coefficients are stored in two different sensitivity matrices in memory. For a change in conductor spatial position, the sensitivity matrices are altered which is estimated for each group and then validated by comparison. Errors in the reconstruction process are minimized by sensor placement at optimal points which ensures the condition number remains close to unity.
    Type: Grant
    Filed: March 18, 2017
    Date of Patent: August 20, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Qi Huang, Arsalan Habib Khawaja, Ai Zheng, Shi Jing, Jian Li, Zhenyuan Zhang, Jianbo Yi
  • Patent number: 10374506
    Abstract: An adaptive control method for zero voltage switching belongs to the field of integrated circuit. In the present invention, the difference between the turn-on time of the power tube and the time of the lowest drain voltage of the power tube in the switching cycle is quantified by the reversible counter, and the quantized result is transmitted to the next switching cycle to adjust the turn-on time of the power tube through the final count result of the reversible counter, so that the power tube after being adjusted can be turned on when the drain voltage of the power tube is the lowest, thus reducing the switching loss. The present invention can adaptively turn on the power tube when the drain voltage of the power tube reaches minimum, thus, realizing the zero-voltage switching, reducing the switching loss of the switching power supply, widening the application range.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: August 6, 2019
    Assignee: University of Electronics Science and Technology of China
    Inventors: Ze-kun Zhou, Jun-Lin Qian, Xiao-Lin Liu, Yue Shi, Zhuo Wang, Bo Zhang
  • Publication number: 20190237576
    Abstract: A power semiconductor device including a first conductivity type semiconductor substrate, a drain metal electrode, a first conductivity type semiconductor drift region, and a second conductivity type semiconductor body region. The second conductivity type semiconductor body region includes a first conductivity type semiconductor source region and anti-punch-through structure; the anti-punch-through structure is a second conductivity type semiconductor body contact region or metal structure; the lower surface of the anti-punch-through structure coincides with the upper surface of the first conductivity type semiconductor drift region or the distance between the two is less than 0.5 ?m, so that make the device avoid from punch-through. An anti-punch-through structure is introduced at the source end of the device to avoid punch-through breakdown caused by short channel and light-doped body region.
    Type: Application
    Filed: April 18, 2018
    Publication date: August 1, 2019
    Applicant: University of Electronic Science and Technology of China
    Inventors: Ming QIAO, Zhengkang WANG, Ruidi WANG, Zhao QI, Bo ZHANG
  • Patent number: 10353417
    Abstract: A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage Vfb. The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor MP is connected to the output terminal of the error amplifier, the source terminal of the power transistor MP is connected to an input voltage VIN, and the drain terminal of the power transistor MP is grounded.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 16, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Xin Ming, Jiahao Zhang, Wenlin Zhang, Di Gao, Xuan Zhang, Zhuo Wang, Bo Zhang
  • Patent number: 10349400
    Abstract: This invention relates to the field of communication technology, and particularly to a communication exchange mechanism design based on frequency hopping, which is applicable to cognitive radio networks. A method for generating hopping frequency sequences for multi-transceiver cognitive radio networks is provided, so as to realize the optimization and tradeoff of the five performance parameters, i.e. DoR, MTTR, ATTR, CL, and NSS. That, is, for a given DoR, the frequency-hopping system should minimize the NSS of the clock synchronous and asynchronous frequency-hopping systems under the condition of MTTR=ATTR=1 and CL<1. The frequency-hopping system of the present invention can use a minimal number of transceivers at each cognitive node to ensure that any two cognitive nodes always achieve frequency hopping rendezvous in each timeslot under the limiting conditions of a certain anti-jamming ability against the primary users and a certain degree of the most serious collisions of control information exchange.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: July 9, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Xuesong Tan, Jieran Wang, Yifan Wang
  • Patent number: 10340373
    Abstract: The present invention relates to the technical field of the power semiconductor device relates to a reverse conducting insulated gate bipolar transistor (RC-IGBT). The RC-IGBT comprises a P-type region, an N-type emitter region, a P-type body contact region, a dielectric trench, a collector region, and an electrical filed cutting-off region. The beneficial effect of the present invention is that, when compared with traditional RC-IGBT, the IGBT of the present invention can eliminate negative resistance effect and effectively improve the performance of forward and reverse conduction.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 2, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Xiaorong Luo, Gaoqiang Deng, Kun Zhou, Qing Liu, Linhua Huang, Tao Sun, Bo Zhang
  • Patent number: 10333468
    Abstract: A terahertz wave fast modulator based on coplanar waveguide combining with transistor is disclosed. The terahertz waves are inputted through a straight waveguide structure, and then are coupled through a probe structure onto a core part of the present invention, which includes a suspended coplanar waveguide structure and a modulation unit with high electron mobility transistor, wherein the suspended coplanar waveguide structure is formed by three metal wires and a semiconductor substrate; and the modulation unit with high electron mobility transistor is located between adjacent metal transmission strips of the coplanar waveguide structure. Transmission characteristics of the terahertz waves in the coplanar waveguide structure are changed through the switching on/off of the modulation unit, so as to fast modulate the amplitudes and phases of the terahertz waves, and finally the modulated terahertz waves are transmitted through a probe—waveguide structure.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 25, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Yaxin Zhang, Han Sun, Yuncheng Zhao, Shixiong Liang, Ziqiang Yang
  • Patent number: 10334032
    Abstract: The present invention discloses an energy-saving deployment method of a virtual CDN. According to the historical flow data of the virtual CDN and the prediction model (ARIMA) in the controller, the network peak flow in the next time period is predicted. Next, the scale of the virtual CDN system at the next moment is calculated according to the peak flow. Meanwhile, several redundant servers are added to correct the prediction error. The network flow is aggregated to the desired virtual servers based on the calculation of the controller through a load balancer. In this way, the utilization rate of the virtual CDN system can be increased, and the energy consumed due to the higher utilization rate of the CDN system is saved.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: June 25, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Gang Sun, Dan Liao, Dongcheng Zhao, Guanghua Yang, Hongfang Yu
  • Patent number: 10331491
    Abstract: A virtual data center (VDC) resource mapping method and device. The method includes: a) receiving a VDC resource request, where the VDC resource request carries a virtual machine distribution identifier, and the virtual machine distribution identifier is used to indicate a maximum quantity K of virtual machines that can be borne by a single physical server; b) selecting, from an unmapped virtual machine set Q in the VDC resource request, M virtual machines to form a partition P; c) selecting a target physical server that can provide a physical resource required by the partition P, and mapping the partition P to the target physical server; and d) removing, from the set Q, the M virtual machines on which resource mapping has been performed, and repeatedly performing steps b), c), and d) until no virtual machine on which resource mapping has not been performed exists in the set Q.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 25, 2019
    Assignees: Huawei Technologies Co., Ltd., University of Electronic Science and Technology of China
    Inventors: Jiao Wang, Cheng Zuo, Hongfang Yu
  • Publication number: 20190148810
    Abstract: The present disclosure is related to the microwave measuring field, and in particularly to a coaxial resonant cavity and system and method for measuring the dielectric constant of material. The coaxial resonant cavity includes a coupling mechanism and a cavity body. The coupling mechanism is accommodated in the cavity body for exciting or coupling microwaves inside the cavity body. The coaxial resonant cavity further includes a probe extending out of the cavity body and being coaxial with the cavity body. The cavity body is shaped as an annular column, and a ratio of an outer radius of the annular column to an inner radius of the annular column is (3-5): 1. The present disclosure still provides a system and method for measuring the dielectric constant of material using the coaxial resonant cavity.
    Type: Application
    Filed: July 19, 2017
    Publication date: May 16, 2019
    Applicant: University of Electronic Science and Technology of China
    Inventors: Yong XIANG, Cong WANG, Xuesong FENG, Fenfen LIU
  • Patent number: 10274376
    Abstract: A system for testing thermal response time of an uncooled infrared focal plane detector array and a method therefor is provided. The system comprises: a blackbody, a chopper, a detector unit under test and a testing system. The method comprises: emitting radiation by the blackbody, chopping by the chopper, then radiating the radiation to the uncooled infrared focal plane detector array under test; generating different responses on the radiation at different chopping frequencies by the uncooled infrared focal plane detector array under test; collecting different response values of the uncooled infrared focal plane detector array under test at different chopping frequencies; obtaining response amplitude at a corresponding frequency in a frequency domain by FFT; fitting according to a formula Rv ? ( f ) = Rv ? ( 0 ) 1 + ( 2 ? ? ? ? f ? ? ? ) 2 to obtain the thermal response time.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: April 30, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Ziji Liu, Shengchen Zhao, Zhiqing Liang, Hongbo Zhang, Tao Wang, Yadong Jiang
  • Patent number: 10251058
    Abstract: A cross layer authentication method based on radio frequency fingerprint, it includes the following steps: S1. In the first time slot, the legitimate transmitter A sends the first packet to the legitimate receiver B, and then B identifies the first data packet by the upper layer authentication; S2. The legitimate recipient B extracts the RF fingerprint eigenvector of the legitimate sender A, and stores it in the memory of the legitimate receiver B; S3. In the next time slot, the sender X sends the second packet to the legitimate receiver B, and the legitimate recipient B extracts the RF fingerprint eigenvector of the sender X; S4. Set sample of the RF fingerprint eigenvector; S5. legitimate receiver B estimates the similarity between the RF fingerprint eigenvector of the sender X and sample of the RF fingerprint eigenvector. This invention is in advantage of low computational complexity, small delay and high precision.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: April 2, 2019
    Assignee: University of Electronic Science and Technology of China
    Inventors: Hong Wen, Jinling Zhang, Runfa Liao, Jie Tang, Fei Pan
  • Patent number: 10236841
    Abstract: A differential amplifier includes a pre-driver stage, an input balun, a matching network, a differential transistor pair, a bias network and an output balun. An output terminal of the pre-driver stage is connected to an input terminal of the input balun. An output terminal of the input balun is connected to the matching network. An output terminal of the matching network is connected to an input terminal of the differential transistor pair and to the bias network. An output terminal of the differential transistor pair is connected to the output balun. A single-turn laminated transformer is used as the input balun of the present invention, and the output balun is of a structure having an inner full frame and an outer half frame, thereby making the differential amplifier have small occupation area, low loss, high operating frequency and high power amplification efficiency.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: March 19, 2019
    Assignee: University of Electronic Science and Technology
    Inventors: Yuehang Xu, Wei Xiao, Xiansuo Liu, Bowen Sun
  • Publication number: 20190080035
    Abstract: The present invention provides a method for equivalent high sampling rate FIR filtering based on FPGA, first, the coefficients h(k) of FIR filter are found by using MATLAB, multiplied by an integer and then rounded for the purpose that the rounded coefficients h(k) can be directly used into a FPGA, then the ADC's output of high data rate fs is lowered by dividing the ADC's output x(n) into M parallel data streams xi(n) of low data rate, and the M×L samples in one clock circle is obtained by delaying the M parallel data streams xi(n) simultaneously by 1, 2, . . . , L? periods of the synchronous clock, at last, the samples yi(n) of FIR filtering output is calculated according to the samples selected from the M×L samples, and the filtered data y(n) of data rate fs is obtained by putting the samples yi(n) together in ascending order of i. Thus, the continuous FIR filtering of an ADC's output sampled with high sampling rate is realized, while the data rates before and after the FIR filtering are unchanged.
    Type: Application
    Filed: October 18, 2018
    Publication date: March 14, 2019
    Applicant: University of Electronic Science and Technology of China
    Inventors: Lianping GUO, Hao ZENG, Feng TAN, Duyu QIU, Xianggong GUO, Yu LI
  • Publication number: 20190067415
    Abstract: A junction termination with an internal field plate, the field plate structure and the junction termination extension region are folded inside the device to make full use of the thickness of the drift region in the body, thereby reducing the area of the termination and relieving the electric field concentration at the end of the PN junction. The breakdown position is transferred from the surface into the body of the original PN junction, and the withstand voltage of termination can reach to the breakdown voltage of the parallel plane junction. Under such design, a smaller area can be obtained than that of the conventional structure at the same withstand voltage.
    Type: Application
    Filed: September 17, 2016
    Publication date: February 28, 2019
    Applicants: University of Electronic Science and Technology of China, Institute of Electronic and Information Engineering of UESTC in Guangdong
    Inventors: Min REN, Yumeng ZHANG, Cong DI, Jingzhi XIONG, Zehong LI, Jinping ZHANG, Wei GAO, Bo ZHANG
  • Publication number: 20190036214
    Abstract: An antenna for generating an arbitrarily directed Bessel beam, including a beam-forming plane and a feeding horn, the beam-forming plane is a dual-layer dielectric substrate structure having a beam focusing function, including: a printed circuit bottom layer, a high-frequency dielectric substrate lower layer, a printed circuit middle layer, a high-frequency dielectric substrate upper layer, and, a printed circuit upper layer; the printed circuit bottom layer, the high-frequency dielectric substrate lower layer, the printed circuit middle layer, the high-frequency dielectric substrate upper layer, and the printed circuit upper layer are co-axially stacked from the bottom to the top: the beam-forming plane is entirely divided into periodically arranged beam-forming units by a plurality of meshes, and each beam-forming unit consists of printed circuit upper, middle and lower metal patches of which centers are on the same longitudinal axis, the high-frequency dielectric substrate lower layer and the high-frequenc
    Type: Application
    Filed: April 23, 2018
    Publication date: January 31, 2019
    Applicant: University of Electronic Science and Technology of China
    Inventors: Yujian CHENG, Yichen ZHONG, Renbo HE, Yan LIU, Yong FAN, Kaijun SONG, Bo ZHANG, Xianqi LIN, Yonghong ZHANG
  • Publication number: 20190021075
    Abstract: This invention relates to the field of communication technology, and particularly to a communication exchange mechanism design based on frequency hopping, which is applicable to cognitive radio networks. A method for generating hopping frequency sequences for multi-transceiver cognitive radio networks is provided, so as to realize the optimization and tradeoff of the five performance parameters, i.e. DoR, MTTR, AITR, CL, and NSS. That, is, for a given DoR, the frequency-hopping system should minimize the NSS of the clock synchronous and asynchronous frequency-hopping systems under the condition of MTTR=ATTR=1 and CL<1. The frequency-hopping system of the present invention can use a minimal number of transceivers at each cognitive node to ensure that any two cognitive nodes always achieve frequency hopping rendezvous in each timeslot under the limiting conditions of a certain anti-jamming ability against the primary users and a certain degree of the most serious collisions of control information exchange.
    Type: Application
    Filed: December 11, 2017
    Publication date: January 17, 2019
    Applicant: University of Electronic Science and Technology of China
    Inventors: Xuesong TAN, Jieran WANG, Yifan WANG
  • Publication number: 20190004553
    Abstract: A ripple pre-amplification based fully integrated LDO pertains to the technical field of power management. The positive input terminal of a transconductance amplifier is connected to a reference voltage Vref, and the negative input terminal of the transconductance amplifier is connected to the feedback voltage Vfb. The output terminal of the transconductance amplifier is connected to the negative input terminal of a transimpedance amplifier and the negative input terminal of an error amplifier. The positive input terminal of the transimpedance amplifier is connected to the ground GND, and the output terminal of the transimpedance amplifier is connected to the positive input terminal of the error amplifier. The gate terminal of the power transistor MP is connected to the output terminal of the error amplifier, the source terminal of the power transistor MP is connected to an input voltage VIN, and the drain terminal of the power transistor MP is grounded.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 3, 2019
    Applicants: University of Electronic Science and Technology of China, Institute of Electronic and Information Engineerin g of UESTC in Guangdong
    Inventors: Xin MING, Jiahao ZHANG, Wenlin ZHANG, Di GAO, Xuan ZHANG, Zhuo WANG, Bo ZHANG
  • Publication number: 20180364315
    Abstract: An electronic current transformer for measuring currents includes a shielding structure, TMR sensor, conductor, amplification circuit, and circuit board. The shielding structure comprises a material that protects the sensor from external disturbance and damps the magnetic field from the internal conductor. The TMR sensor is connected to the amplification circuit for electric current measurement by means of reconstruction of magnetic field measurement. The TMR sensor is configured to receive data from the conductor and to transmit the data to the amplification circuit, which is configured to amplify the data and release the data as an output of the transformer.
    Type: Application
    Filed: November 27, 2017
    Publication date: December 20, 2018
    Applicant: University of Electronic Science and Technology of China
    Inventors: Qi Huang, Arsalan Habib Khawaja, Yafeng Chen, Shi Jing, Jian Li, Zhenyuan Zhang, Jianbo Yi
  • Patent number: 10146238
    Abstract: A resistorless CMOS low power voltage reference circuit is provided. The start-up circuit is used to prevent the circuit to stay in the zero state and stop working when the circuit gets out of the zero state. The self-biased VPTAT generating circuit generate the voltage VPTAT which has positive temperature coefficient. The square-law current generating circuit generates a square-law current which is proportional to ?T2 through the VPTAT. Finally, the reference voltage VREF is obtained by introducing the square-law current into the reference voltage output circuit. The reference voltage VREF of this application can realize approximative zero temperature coefficient in the temperature range of ?40° C.˜100° C. This application improves temperature characteristic which may be poorer due to temperature nonlinearity of carrier mobility based on the traditional subthreshold reference. This application can reduce the power consumption from ?W level to nW level and realize low power consumption.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: December 4, 2018
    Assignee: University of Electronic Science and Technology of China
    Inventors: Zekun Zhou, Yao Wang, Jianwen Cao, Hongming Yu, Yunkun Wang, Anqi Wang, Zhuo Wang, Bo Zhang