Abstract: A sorting method of data documents is provided, adapted to an electronic device. The sort method includes the following steps: retrieving a plurality of keywords from contents of a plurality of data documents; retrieving corresponding keyword rankings of the plurality of keywords by a search engine; searching corresponding keyword categories of the plurality of keywords; and generating a sort algorithm based on the plurality of keywords, the keyword ranking and the keyword category of each of the plurality of keywords, and a current ranking of each of the plurality of data documents, wherein the sort algorithm is used to calculate a predicting ranking of another data document and to sort the another data document.

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract: A method that compensates for misalignment on a synchronous data bus. The method includes: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe, receiving a lag pulse signal, and generating a replicated strobe signal by employing the replicated propagation path loads lengths, and buffering; measuring the time between assertion of the lag pulse signal and assertion of the replicated strobe signal; on a lag bus, generating a value that indicates the time; within a synchronous lag receiver, receiving a first one of a plurality of radially distributed strobes and a data bit, and delaying registering of the data bit by the time.

Abstract: A method for aligning signals on a bus, including: replicating propagation path lengths, loads, and buffering of a radial distribution network for a strobe; receiving a first signal, and generating a second signal by employing the replicated propagation path lengths, loads, and buffering; receiving control information over a standard JTAG bus, wherein the control information indicates an amount to adjust a propagation time; and measuring the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, said measuring comprising: selecting one of a plurality of successively delayed versions of the first signal that coincides with assertion of the second signal; adjusting the propagation time by the amount prescribed by the control information to yield an adjusted propagation time; and gray encoding the adjusted propagation time to generate a value on a lag bus.

Abstract: An apparatus including a ROM, an event detector, and a tamper detector. The ROM has BIOS contents stored as plaintext, and an encrypted digest. The encrypted digest is an encrypted version of a first digest corresponding to the BIOS contents. The event detector generates an interrupt that interrupts operation of the system upon occurrence of an event. The tamper detector is operatively coupled to the ROM and accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs a microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second message digest with the decrypted message digest, and precludes the operation of the microprocessor if the second digest and the decrypted digest are not equal.

Abstract: A microprocessor includes an indicator and a plurality of processing cores. Each of the plurality of processing cores is configured to sample the indicator. When the indicator indicates a first predetermined value, the plurality of processing cores are configured to collectively designate a default one of the plurality of processing cores to be a bootstrap processor. When the indicator indicates a second predetermined value distinct from the first predetermined value, the plurality of processing cores are configured to collectively designate one of the plurality of processing cores other than the default processing core to be the bootstrap processor.

Abstract: A circuit substrate includes a base layer, a first patterned conductive layer, a dielectric layer, a conductive block and a second patterned conductive layer. The first patterned conductive layer is disposed on the base layer and has a first pad. The dielectric layer is disposed on the base layer and covers the first patterned conductive layer, wherein the dielectric layer has an opening and the first pad is exposed by the opening. The conductive block is disposed in the opening and covers the first pad. The second patterned conductive layer is disposed on a surface of the dielectric layer and has a second pad, wherein the second pad and the conductive block are integrally formed.

Abstract: Data checking and correction for a volatile memory of a data storage device, the data storage device further including a non-volatile memory and a controller. The controller operates the non-volatile memory in accordance with requests issued from a host. The controller uses the volatile memory for temporary storage of temporary data required for operations of the non-volatile memory. The controller generates error checking and correction content for the temporary data and writes the temporary data and the error checking and correction content into the volatile memory in at least one burst length for temporary storage of the temporary data. In this manner, it is not necessary to manufacture any additional pin on the volatile memory for data checking and correction.

Abstract: A microprocessor includes a plurality of semiconductor dies, a bus coupling the plurality of semiconductor dies, and a plurality of processing cores. A distinct subset of the processing cores is located on each of the semiconductor dies. Each die comprises a control unit configured to selectively control a respective clock signal to each of the subset of cores of the die. For each core of the subset, in response to the core writing a value to the control unit, the control unit is configured to turn off the respective clock signal to the core and to write the value over the bus to the control unit of the other die. Collectively all of the control units are configured to simultaneously turn on the clock signals to all of the processing cores after the clock signals have been turned off to all of the processing cores.

Abstract: The present application provides an interference estimation circuit which includes a signal generator, a first symbol extractor and a first mixer. The signal generator generates an orthogonal signal orthogonal to partial symbols of a plurality of pilot signals. The first symbol extractor extracts partial symbols of a first decoded signal decoded from a received signal wherein the first decoded signal contains one of the plurality of pilot signals, and includes an input node for receiving the first decoded signal and an output node for outputting a first extracted signal. The first extracted signal is substantially orthogonal to the orthogonal signal. The first mixer is coupled to the signal generator for receiving the orthogonal signal and to the first symbol extractor for receiving the first extracted signal, and outputs a first mixed signal of the orthogonal signal and the first extracted signal for interference estimation.

Abstract: A memory chip coupled to a host includes a memory and a controller. Multiple boot images having the same content are pre-loaded in the memory. The controller is coupled to the memory for processing data transmission between the memory chip and the host. The controller further determines whether the memory chip enters a boot mode for the first time. When the memory chip enters the boot mode for the first time, the controller accesses the memory so as to obtain a correct boot image from the boot images and transmits the correct boot image to the host.

Abstract: An apparatus including a ROM and a microprocessor. The ROM includes BIOS contents that are stored as plaintext and an encrypted digest. The encrypted digest includes an encrypted version of a first digest corresponding to the BIOS contents. The microprocessor is coupled to the BIOS ROM, and includes a tamper timer and a tamper detector. The tamper timer periodically generates an interrupt at a prescribed interval. The tamper detector accesses the BIOS contents and the encrypted digest upon assertion of the interrupt, and directs the microprocessor to generate a second digest corresponding to the BIOS contents and a decrypted digest corresponding to the encrypted digest using the same algorithms and key that were employed to generate the first digest and the encrypted digest, and compares the second digest with the decrypted digest, and precludes operation of the microprocessor if the second digest and the decrypted digest are not equal.

Abstract: A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

Abstract: A superscalar pipelined microprocessor includes a register set defined by its instruction set architecture, a cache memory, execution units, and a load unit, coupled to the cache memory and distinct from the other execution units. The load unit comprises an ALU. The load unit receives an instruction that specifies a memory address of a source operand, an operation to be performed on the source operand to generate a result, and a destination register of the register set to which the result is to be stored. The load unit reads the source operand from the cache memory. The ALU performs the operation on the source operand to generate the result, rather than forwarding the source operand to any of the other execution units of the microprocessor to perform the operation on the source operand to generate the result. The load unit outputs the result for subsequent retirement to the destination register.

Abstract: A circuit substrate has the following elements. A stacked circuit structure has a first surface and a second surface opposite thereto surface. A first patterned inner conductive layer is disposed on the first surface and has multiple pads. A first patterned outer conductive layer is disposed on the patterned inner conductive layer and has multiple conductive pillars, wherein each of the first conductive pillar is located on the corresponding first pad. The first dielectric layer covers the first surface, the first patterned inner conductive layer and the first patterned outer conductive layer, and has multiple first concaves, wherein the first concave exposes the top and side of the corresponding first conductive pillar. A semiconductor package structure applied the above circuit substrate and a process for fabricating the same are also provided here.

Abstract: A microprocessor includes a plurality of processing cores each comprises a corresponding memory physically located inside the core and readable by the core but not readable by the other cores (“core memory”). The microprocessor also includes a memory physically located outside all of the cores and readable by all of the cores (“uncore memory”). For each core, the uncore memory and corresponding core memory collectively provide M words of storage for microcode instructions fetchable by the core as follows: the uncore memory provides J of the M words of microcode instruction storage, and the corresponding core memory provides K of the M words of microcode instruction storage. J, K and M are counting numbers, and M=J+K. The memories are non-architecturally-visible and accessed using a fetch address provided by a non-architectural program counter, and the microcode instructions are non-architectural instructions that implement architectural instructions.

Abstract: A microprocessor includes a first hardware data prefetcher that prefetches data into the microprocessor according to a first algorithm. The microprocessor also includes a second hardware data prefetcher that prefetches data into the microprocessor according to a second algorithm, wherein the first and second algorithms are different. The second prefetcher detects that it is prefetching data into the microprocessor according to the second algorithm in excess of a first predetermined rate and, in response, sends a throttle indication to the first prefetcher. The first prefetcher prefetches data into the microprocessor according to the first algorithm at below a second predetermined rate in response to receiving the throttle indication from the second prefetcher.

Abstract: A bridging device and a power saving method thereof are disclosed. When a bridging chip of the bridging device receives a power saving command transferred from a host and thereby enters a power saving state, a voltage converter of the bridging device is disabled accordingly and a selection circuit selects to couple a bus voltage to the bridging chip to power the bridging chip. The bus voltage is transferred from the host through a power pin of a connector of the bridging device. The connector is coupled to the host.

Abstract: A microprocessor includes a plurality of processing cores, a service processing unit and a memory accessible by both the service processing unit and the plurality of processing cores. At least one of the plurality of processing cores is configured to write a patch to the memory. The patch comprises one or more instructions to be fetched from the memory and executed by the service processing unit after written to the memory by the at least one of the plurality of processing cores.

Abstract: A microprocessor includes a control unit configured to selectively control a respective clock signal to each of a plurality of processing cores. Each of the processing cores is configured to separately write a value to the control unit. For each core of the plurality of processing cores, the control unit is configured to turn off the respective clock signal to the core in response to the core writing a value to the control unit. The control unit is configured to detect a condition has occurred when all of the processing cores have written a value to the control unit and the control unit has turned off the respective clock signal to all of the processing cores. The control unit is configured to simultaneously turn on the respective clock signal to all of the processing cores in response to detecting the condition has occurred.