Abstract: An apparatus includes a fuse array and a plurality of cores. The fuse array is programmed with compressed data. Each of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed data, and to store decompressed data sets for one or more cache memories within the each of the plurality of cores in a stores that is coupled to the each of the plurality of cores. Each of the plurality of cores has reset logic and sleep logic. The reset logic employs the decompressed data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic determines that power is restored following a power gating event, and subsequently accesses the stores to retrieve and employ the decompressed data sets to initialize the one or more caches following the power gating event.

Abstract: An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

Abstract: An apparatus includes a fuse array, a stores, and a plurality of cores. The fuse array is programmed with compressed configuration data. The stores is for storage and access of decompressed configuration data sets. One of the plurality of cores accesses the fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store the decompressed configuration data sets for one or more cache memories in the stores. Each of the plurality of cores includes reset logic and sleep logic. The reset logic is configured to employ the decompressed configuration data sets to initialize the one or more cache memories upon power-up/reset. The sleep logic is configured to determine that power is restored following a power gating event, and is configured to subsequently access the stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following the power gating event.

Abstract: A storage media control method, by which a data strobe signal is shifted by different phase shifts at different time intervals during a write-leveling operation to be received by a storage media and compared to a clock signal for returning a data signal. At the storage media side, during the write-leveling operation, a synchronous transmission between the received data strobe signal and the clock signal causes a transition event at the data signal. The number of transition-event occurrences is counted. When the count shows that just one transition event has occurred over a full round of phase shift tests of the data strobe signal, the phase shift corresponding to the transition event is used in the adjustment of the data strobe signal, which is received by the storage media as the data extraction reference of a write operation.

Abstract: A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state.

Abstract: A bridging device and a power saving method thereof are disclosed. The disclosed bridging device includes a connector, a connection detector and a bridging chip. The connector is operative to connect to a host and includes a power pin and a command pin. The connection detector is coupled to the power pin to determine whether the connector is floating, and, outputs a linked signal when the connection is non-floating. The bridging chip is coupled to the command pin and the connection detector. When the bridging chip receives a power saving command transferred from the host via the command pin and the linked signal transferred from the connection detector, the bridging chip executes a power saving operation.

Abstract: A method and system for controlling multiple displays is provided. The disclosed method is used to control a plurality of graphics processing units (GPUs), wherein every GPU controls one or more displays. The method includes the following steps: providing a graphical interface the same to a graphical program library of an operating system to replace the graphical program library to receive a drawing command from an application program; determining a display set of the GPUs according to a display region of the application program, wherein a frame displayed by the display controlled by each GPU is intersected to the display region; and delivering coordinate-transformed drawing commands to the GPUs in the display set according to the display intersection region, wherein each GPU in the display set only draws the content of the corresponding display intersection region.

Abstract: An apparatus including a ROM, a selector, and a detector. The ROM has partitions stored as plaintext, and encrypted digests, each comprising an encrypted version of a first digest associated with a corresponding one of the partitions. The selector selects one or more partitions responsive to an interrupt. The detector generates the interrupt at a combination of intervals and event occurrences, and accesses the one or more partitions and corresponding one or more encrypted digests upon assertion of the interrupt, and directs generation of one or more second digests corresponding to the one or more partitions and one or more decrypted digests corresponding to the one or more encrypted digests using the same algorithms and key used to generate the first digest and encrypted digests, and compares the second digests with the decrypted digests, and precludes the operation if the second digests and the decrypted digests are not pair wise equal.

Abstract: A microprocessor supports an instruction set architecture that specifies: processor modes, architectural registers associated with each mode, and a load multiple instruction that instructs the microprocessor to load data from memory into specified ones of the registers. Direct storage holds data associated with a first portion of the registers and is coupled to an execution unit to provide the data thereto. Indirect storage holds data associated with a second portion of the registers and cannot directly provide the data to the execution unit. Which architectural registers are in the first and second portions varies dynamically based upon the current processor mode. If a specified register is currently in the first portion, the microprocessor loads data from memory into the direct storage, whereas if in the second portion, the microprocessor loads data from memory into the direct storage and then stores the data from the direct storage to the indirect storage.

Abstract: An isolation circuit includes a first multiplexer, a D flip-flop, a second multiplexer, an OR gate, and an AND gate. The first multiplexer selects a data signal or a scan-in signal as a first element output signal according to a scan enable signal. The D flip-flop generates a second element output signal according to the first element output signal. The second element output signal is fed back to the first multiplexer and is used as the data signal. The second multiplexer selects an isolation signal or the second element output signal as a third element output signal according to a test enable signal. The OR gate generates a fourth element output signal according to the scan enable signal and the third element output signal. The AND gate generates a second power domain signal according to a first power domain signal and the fourth element output signal.

Abstract: The invention provides a system and method for decoding and deblocking a video frame having a plurality of macroblocks. The system of the invention comprises a decoder configured to decode the macroblocks, a deblock configured to deblock the macroblocks, and a deblock buffer comprising a plurality of counters corresponding to the plurality of macroblocks respectively. Each counter corresponds to a macroblock group comprising a predetermined amount of neighboring macroblocks. In response to a counter is incremented to a fixed value, the macroblock group corresponds to the counter is deblocked.

Abstract: A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal oscillator has a first terminal and a second terminal. The inverter generates a first signal and a second signal at the first and second terminals of the crystal oscillator, respectively. The first circuit coupled to the first terminal of the crystal oscillator generates a first clock signal with a constant frequency according to the first signal. The second circuit coupled to the second terminal of the crystal oscillator generates a second clock signal with a variable frequency according to the second signal.

Abstract: A voice control device and a corresponding voice control method are provided. The voice control device includes a sound receiver, a sound converter, a voice identifier, and a central processing unit (CPU). The sound receiver receives a first sound signal. The sound converter converts the first sound signal from analog signal to digital signal. The voice identifier identifies a first voice signal from the first sound signal, performs a first comparison on the first voice signal and a second voice signal, and generates a wake-up signal according to the first comparison. When receiving the wake-up signal, the CPU enters a working state from a sleeping state, performs a second comparison on the first voice signal and the second voice signal, and takes over the voice input from the sound receiver and the sound converter according to the second comparison.

Abstract: A microprocessor capable of operating as both an x86 ISA and an ARM ISA microprocessor includes first, second, and third storage that stores x86 ISA-specific, ARM ISA-specific, and non-ISA-specific state, respectively. When reset, the microprocessor initializes the first storage to default values specified by the x86 ISA, initializes the second storage to default values specified by the ARM ISA, initializes the third storage to predetermined values, and begins fetching instructions of a first ISA. The first ISA is the x86 ISA or the ARM ISA and a second ISA is the other ISA. The microprocessor updates the third storage in response to the first ISA instructions. In response to a subsequent one of the first ISA instructions that instructs the microprocessor to reset to the second ISA, the microprocessor refrains from modifying the non-ISA-specific state stored in the third storage and begins fetching instructions of the second ISA.

Abstract: A graphics processing unit (GPU) and a management method of the GPU are provided. The GPU includes at least one graphics engine and an engine manager. The graphics engine performs a video decoding function or a graphics rendering function according to a graphics command from a driver software. The engine manager records a workload index of each graphics engine. The engine manager also adjusts the work ability of one of or more of the at least one graphics engine according to an adjustment command from the driver software. The driver software provides the adjustment command according to the workload index.

Abstract: A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program and a plurality of hardware registers. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, the plurality of hardware registers store x86 ISA architectural state; when the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, the plurality of hardware registers store ARM ISA architectural state.

Abstract: A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate is disclosed. A first conductive line and a second conductive line are disposed in the first insulating layer, and each of the first and second conductive lines has a first end and a second end, wherein the second ends of the first and second conductive lines are coupled to each other. A first winding portion and a second winding portion are disposed in the second insulating layer, and each of the first and second winding portions includes a third conductive line and a fourth conductive line arranged from the inside to the outside. Each of the third and fourth conductive lines has a first end and a second end, wherein the first and second conductive lines overlap at least a portion of the third conductive lines.

Abstract: A controlling device applied to a touch panel. The controlling device includes a sampling module, a determining module and a reporting module. The sampling module samples electrical signals of the touch panel, and generates at least one trigger signal corresponding to the at least one touch event when at least one touch event occurs on the touch panel. The determining module determines whether the at least one touch event is a single-point-multi-finger gesture according to a position of the at least one trigger signal and sampled physical quantity. The reporting module reports the at least one touch event when the determining module determines that the at least one touch event corresponding to the at least one trigger signal is the single-point-multi-finger gesture.

Abstract: The disclosure provides an unlock method of an electronic system with a touch screen. The unlock method includes steps below: receiving a triggering event when the system is locked; activating the touch screen in response to the event; receiving an input gesture; comparing the gesture with a customized gesture; unlocking the system in case that the input gesture is matched to the customized gesture, which is customized by user, and is not a default unlock gesture built in the electronic system.

Abstract: A system and a method for assigning virtual functions, and a management host thereof are provided. The management host is connected with a computer host through a bridge and has at least one virtual function. A management processor of the management host updates a mapping table according to a virtual function establishing request to assign the at least one virtual function to the computer host according to the mapping table, wherein the management processor determines whether to establish the virtual function according to the mapping table. The management processor transmits a hot-plug event to the corresponding computer host via a switch according to an assignment result and connects the virtual function with the corresponding computer host to dynamically adjust an allocation of the virtual function.