Abstract: A power-management method is provided, and the power-management method includes setting a central processing unit in a first low-power state when receiving a second low-power state request requiring the central processing unit to enter the second low-power state, obtaining first idle periods of the peripheral modules respectively to determine a second idle period according to the first idle periods of the peripheral modules, determining whether the peripheral modules have not sent a data-access request during the second idle period, setting the central processing unit in the second low-power state when the peripheral modules have not sent the data-access request during the second idle period, wherein each first idle period is an interval period between two data transmissions of each peripheral module.

Abstract: A microprocessor includes hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. The microprocessor also includes hardware registers that instantiate the ARM Architecture GPRs. In response to an ARM MRRC instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate two of the ARM GPRs registers. In response to an ARM MCRR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate two of the ARM Architecture GPRs registers. The hardware registers may be shared by the two Architectures.

Abstract: An embodiment of the invention provides a secure boot method for an electronic device including an embedded controller and a processor. The method includes the steps of verifying a secure loader by the embedded controller, unlocking a peripheral hardware of the electronic device by the embedded controller, and executing the secure loader by the processor.

Abstract: An adaptive universal serial bus (USB) charging method and system are disclosed. In a low-power state, a USB device is charged with a non-USB charging mode. The non-USB charging mode is retained when no variation of a data signal coupled to the USB device is detected. When the data signal possesses variation for a first period, it is switched to a third proprietary charging mode.

Abstract: A microprocessor processes conditional non-branch instructions that specify a condition and instruct the microprocessor to perform an operation if the condition is satisfied and otherwise to not perform the operation. A predictor provides a prediction about a conditional non-branch instruction. An instruction translator translates the conditional non-branch instruction into a no-operation microinstruction when the prediction predicts the condition will not be satisfied, and into a set of one or more microinstructions to unconditionally perform the operation when the prediction predicts the condition will be satisfied. An execution pipeline executes the no-operation microinstruction or the set of microinstructions. The predictor translates into a second set of one or more microinstructions to conditionally perform the operation when the prediction does not make a prediction.

Abstract: A progress recording method and a corresponding recovering method adapted to an encoding operation performed on a storage area of a storage device are provided. The progress recording method includes the following steps. A variable set is initialized and stored. The encoding operation includes a plurality of sub-operations, and each of the sub-operations is corresponding to at least one flag variable in the variable set. The flag variables are used for recording execution progresses of the sub-operations. When each of the sub-operations is executed, the corresponding flag variable in the variable set is updated according to the execution progress of the sub-operation.

Abstract: Methods for accessing hardware resources in an electronic device with a browser-based operating system (OS) which includes a user interface running in a browser are provided. A local server is first provided on the electronic device, wherein the local server has a corresponding URL and a dedicated network port. Then, upon receiving a service request from the client-side web application, the local server analyzes a service type of the service request and performs an operation to at least one of the hardware resources corresponding to the service type, wherein the service request is generated and directed to the local server according to the URL and the dedicated network port of the local server by the client-side web application on the electronic device.

Abstract: A microprocessor includes a first and second hardware data prefetchers configured to prefetch data into the microprocessor according to first and second respective algorithms, which are different. The second prefetcher is configured to detect a memory access pattern within a memory region and responsively prefetch data from the memory region according the second algorithm. The second prefetcher is further configured to provide to the first prefetcher a descriptor of the memory region. The first prefetcher is configured to stop prefetching data from the memory region in response to receiving the descriptor of the memory region from the second prefetcher. The second prefetcher also provides to the first prefetcher a communication to resume prefetching data from the memory region, such as when the second prefetcher subsequently detects that a predetermined number of memory accesses to the memory region are not in the memory access pattern.

Abstract: A low-offset bandgap circuit including a core bandgap circuit and an offset-cancelling circuit is provided. The low-offset bandgap circuit provides a reference voltage at an output node. The core bandgap circuit includes a core operational amplifier to generate a core current. The offset-cancelling circuit is coupled to two input terminals of the core operational amplifier. The offset-cancelling circuit is configured to generate a compensation current according to the voltages at the two input terminals of the core operational amplifier so as to compensate for an offset voltage of the core operational amplifier. The reference voltage is generated according to the core current and the compensation current.

Abstract: A method for MAC address management is provided. A MAC address is provided, and capacities of a first column and a second column corresponding to a first index in a MAC table are checked. If the first column and the second column are filled, capacities of a third column and a fourth column corresponding to a second index in the MAC table are checked. If one of the third and fourth columns is empty, the MAC address is written thereto. The second index is successive to the first index. The MAC table further comprises a plurality of time stamp columns, recording idle time of each MAC address.

Abstract: An instruction translator receives a conditional load/store instruction that specifies a condition, destination/data register, base register, offset source, and memory addressing mode. The instruction instructs the microprocessor to load data from a memory location into the destination register (conditional load) or store data to the memory location from the data register (conditional store) only if the condition flags satisfy the condition. The offset source specifies whether the offset is an immediate value or a value in an offset register. The addressing mode specifies whether the base register is updated when the condition flags satisfy the condition. The instruction translator translates the conditional load instruction into a number of microinstructions, which varies as a function of the offset source, addressing mode, and whether the conditional instruction is a conditional load or store instruction.

Abstract: A video wall, having screens, cables, synchronization detection modules and a central control unit. The cables are operative to carry image data to be displayed on the screens. The synchronization detection modules are coupled between the screens and the cables for detection of a feature symbol. The central control unit collects detection results from the synchronization detection modules, and the detection results are utilized in the adjustment of the image data before cable transmission. In this manner, image display synchronization between the screens is achieved. The synchronization detection modules may be implemented as connectors, each having a first end connected to a screen and a second end connected to a cable.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a serial advanced technology attachment (SATA) physical layer, a clock generator and a control unit. The SATA physical layer is configured to provide connection with an SATA device and perform data transmission with the SATA device is performed at a first clock frequency. The clock generator is configured to provide a clock signal having the first clock frequency to the SATA physical layer. When at least one specific event is detected by the control unit, the control unit controls the clock generator to provide the clock signal having a second clock frequency to the SATA physical layer, so that the SATA physical layer performs data transmission with the SATA device at the second clock frequency. The second clock frequency is lower than the first clock frequency.

Abstract: A non-volatile memory (NVM) apparatus and an operation method thereof are provided. A mapping table in a main memory is divided into a plurality of sub-mapping tables according to logical address groups. When an access command of a host is processed by the NVM apparatus, at least one corresponding sub-mapping table is selected from the sub-mapping tables according to a logical address of the access command. If the at least one corresponding sub-mapping table is required to be rebuilt, then the at least one corresponding sub-mapping table is rebuilt, and the logical address of the access command is converter for accessing the NVM apparatus according to the at least one corresponding sub-mapping table which has been rebuilt.

Abstract: Graphics processing units (GPUs) are used, for example, to process data related to three-dimensional objects or scenes and to render the three-dimensional data onto a two-dimensional display screen. One embodiment, among others, of a unified cache system used in a GPU comprises a data storage device and a storage device controller. The data storage device is configured to store graphics data processed by or to be processed by one or more shader units. The storage device controller is placed in communication with the data storage device. The storage device controller is configured to dynamically control a storage allocation of the graphics data within the data storage device.

Abstract: Disclosed are various embodiments for providing networked applications that are segmented into multiple client-cached executable modules. Multiple networked applications are provided by an application server, and a module cache is maintained in a client. The client obtains a user invocation of a particular functionality associated with a networked application. One of the modules associated with the particular functionality is obtained by the client from the application server over a network in response to determining that the module is not already in the module cache. The module is executed by the client to provide the particular functionality. A data cache may be implemented that includes data blocks that have been used, are being used, or are predicted to be used by the networked application.

Abstract: A transmission circuit including an equalizer circuit, a slicer circuit, a signal detection circuit, and a control circuit is provided. The equalizer circuit performs an equalizing operation on an input signal according to preset states to output an equalizing signal corresponding to each preset state. The slicer circuit performs a slicing operation on the equalizing signal to output a slicing signal. The signal detection circuit detects and compares the equalizing signal and the slicing signal and accordingly adjusts the equalizer circuit to one of the preset states. The control circuit receives the slicing signal corresponding to each preset state, compares the slicing signal corresponding to each preset state with a plurality of signal patterns to generate a comparison result, and selects one of the preset states according to the comparison result, such that the control circuit let the equalizer circuit perform the equalizing operation according to the selected preset state.

Abstract: A circuit layout structure is suitable for a circuit board and includes following components. A first differential pair and a second differential pair respectively extend from the inside of a chip area of the circuit board to the outside of the chip area through a first patterned conductive layer of the circuit board, and respectively extend between the chip area and a port area of the circuit board through a second patterned conductive layer of the circuit board. A third differential pair extends from the chip area to the port area through the first patterned conductive layer. A first ground plane is constituted by the first patterned conductive layer. Orthogonal projections of the first differential pair and the second differential pair on the second patterned conductive layer overlap the first ground plane.

Abstract: Included are embodiments for processing video data. At least one embodiment includes a logic configured to receive video data having a format chosen from at least two formats and logic configured to receive an instruction from an instruction set including an indication of the format of the video data. Some embodiments include first parallel logic configured to process video data according to a first format in response to the indication is the first format and second parallel logic configured to process the video data according to a second format in response to the indication is the second format.

Abstract: An apparatus includes a fuse array and a stores. The fuse array is disposed on a die, and is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompresses the compressed configuration data, and stores a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores, and where, following a power gating event, one of the each of the plurality of cores subsequently accesses a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the caches.