Abstract: A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.

Abstract: An apparatus including a BIOS read only memory (ROM) and a tamper detector. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest comprising an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is coupled to the BIOS ROM, and accesses the BIOS contents and the encrypted message digest upon reset of a microprocessor, and directs the microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the same algorithms and key that were employed to generate the first message digest and the encrypted message digest, and compares the second message digest with the decrypted message digest, and precludes the operation of the microprocessor if the second message digest and the decrypted message digest are not equal.

Abstract: A microprocessor includes one or more memories configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed. A method includes receiving from a memory a first N-bit wide microcode word, determining whether or not a predetermined portion of the first N-bit wide microcode word is a predetermined value, if the predetermined portion is not the predetermined value, decompressing the first N-bit wide microcode word to generate an M-bit wide microcode word, and if the predetermined portion is the predetermined value, receiving from the memory a second N-bit wide microcode word and joining portions of the first and second N-bit wide microcode words to generate the M-bit wide microcode word.

Abstract: A graphics display system is provided with a graphics processing module and a display module. The graphics processing module detects whether first frame data is equal to second frame data subsequent to the first frame data, and in response to the first frame data being equal to the second frame data, stops outputting any frame data after outputting the second frame data and a mode switching command. The display module displays graphic images according to the first frame data, and stores the second frame data as temporary data and continuingly displays the graphic images according to the temporary data in response to the mode switching command.

Abstract: An interface chip capable of accurate link detection. The interface chip mounted on a first electronic device has a link layer and a physical layer. The link layer outputs data to be transformed and transmitted to a second electronic device by the physical layer. The data transmitted from the second electronic device is received and transformed by the physical layer and then conveyed to the link layer. The link layer includes a state machine, which performs a state modification on the first electronic device to rescue the second electronic device from a trapped state for confirming a link between the first and second electronic devices, wherein data output by the link layer and transformed and transmitted to the second electronic device by the physical layer is changed according to the state modification.

Abstract: A method for adjusting color values of a video signal. The video signal includes a first frame and a second frame prior to the first frame. The method includes steps of: determining a motion-level value of a first pixel in the first frame according to color values of the first pixel and a second pixel in the second frame; performing a first filtering operation to obtain an adjusted color value of the first pixel if the motion-level value is smaller than a first threshold; performing a second filtering operation to obtain the adjusted color value of the first pixel if the motion-level value is greater than a first threshold; and performing a third filtering operation to obtain the adjusted color value of the first pixel if the motion-level value lies between the first threshold and the second threshold.

Abstract: PRD (Physical Region Descriptor) pre-fetch methods for DMA (Direct Memory Access) unit are provided. When a DMA out transaction for a memory is performed, it is determined whether a first queue is full or nearly full, wherein the first queue is used to store data corresponding to the DMA out transaction. If the first queue is full or nearly full, at least one PRD entry is read from a first PRD table, and stored to a first cache. When a DMA in transaction for the memory is performed, it is determined whether a second queue is empty or nearly empty, wherein the second queue is used to store data corresponding to the DMA in transaction. If the second queue is empty or nearly empty, at least one PRD entry is read from a second PRD table, and stored to a second cache.

Abstract: A microprocessor includes hardware registers that instantiate the IA-32 Architecture EDX and EAX GPRs and hardware registers that instantiate the Intel 64 Architecture R8-R15 GPRs. The microprocessor associates with each of the R8-R15 GPRs a respective unique MSR address. In response to an IA-32 Architecture RDMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor reads the contents of the hardware register that instantiates the specified one of the R8-R15 GPRs into the hardware registers that instantiate the EDX:EAX registers. In response to an IA-32 Architecture WRMSR instruction that specifies the respective unique MSR address of one of the R8-R15 GPRs, the microprocessor writes into the hardware register that instantiates the specified one of the R8-R15 GPRs the contents of the hardware registers that instantiate the EDX:EAX registers. The microprocessor does so even when operating in non-64-modes.

Abstract: A through-hole layout structure is suitable for a circuit board. The through-hole layout structure includes a pair of first differential through-holes, a pair of second differential through-holes, a first ground through-hole, a second ground through-hole, and a third ground through-hole, which are all arranged on a first line. The first ground through-hole is located between the pair of first differential through-holes and the pair of second differential through-holes. The pair of first differential through-holes is located between the first ground through-hole and the second ground through-hole. The pair of second differential through-holes is located between the first ground through-hole and the third ground through-hole.

Abstract: The invention provides a memory device. The memory device includes a flash memory, a memory, and a controller. The flash memory includes a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a specific requirement, and when the data access fulfills the conditions of the specific requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.

Abstract: A process for fabricating a circuit substrate is provided. The process includes the following steps. A carrier is provided. A conductive layer and a dielectric layer are placed on the carrier, and the conductive layer is located between the carrier and the dielectric layer. The dielectric layer is patterned to form a patterned-dielectric layer having first openings partially exposing the conductive layer. Arc-shaped grooves are formed on the exposed part of the conductive layer. A first-patterned-photoresist layer having second openings respectively connecting the first openings is formed. Conductive structures are formed, wherein each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part; the second openings, the first openings and the arc-shaped grooves are respectively filled with the pad parts, the connection parts and the protruding parts. The first patterned photoresist layer, the carrier and the conductive layer are removed.

Abstract: A recovering method is adapted to an encoding operation performed on a storage area of a storage device. The recovering method includes: reading a variable set, wherein the encoding operation comprises a plurality of sub-operations, and each of the sub-operations is corresponding to at least one flag variable in the variable set; determining whether any one of the sub-operations is interrupted according to the variable set; when one of the sub-operations is interrupted, recovering the sub-operation according to the at least one flag variable corresponding to the sub-operation; and carrying on the encoding operation according to a process recorded by the flag variables in the variable set.

Abstract: An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected from the test clocks. The flash memory is operated in a variable-frequency manner by which the flash memory is switched between the clock candidates, such that electromagnetic interference is spread over different bands.

Abstract: The embodiments disclosed herein provide systems and methods for improved motion estimation using a graphics processing unit. One such embodiment includes a method for determining a motion vector describing motion relative to a reference block, which comprises determining which of a plurality of prediction blocks is a good match with the reference block, according to a match criteria. The method further comprises performing a local area exhaustive search, in an area centered around the good match prediction block, to produce a best match with the reference block. The best match has integral pixel resolution. The method further comprises modeling the degree of match between the best match and the reference block as a quadratic surface and analytically determining a minima of the quadratic surface, corresponding to a best matching block with fractional resolution. The method further comprises computing a fractional motion vector based on the best matching block with fractional resolution.

Abstract: A microprocessor includes a plurality of processing cores each including a hardware instruction translator that translates instructions of x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs into microinstructions defined by a microinstruction set of the microprocessor. The microinstructions are encoded in a distinct manner from the manner in which the instructions of the x86 and ARM instruction sets are defined. Each core includes an execution pipeline that executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions. Each core uses and associated indicator to determine whether it will boot as an x86 ISA core or an ARM ISA core when reset. The indicators are configurable to indicate that at least one of the cores will boot as an x86 ISA core and at least one other of the cores will boot as an ARM ISA core.

Abstract: A microprocessor includes a plurality of registers that holds an architectural state of the microprocessor and an indicator that indicates a boot instruction set architecture (ISA) of the microprocessor as either the x86 ISA or the Advanced RISC Machines (ARM) ISA. The microprocessor also includes a hardware instruction translator that translates x86 ISA instructions and ARM ISA instructions into microinstructions. The hardware instruction translator translates, as instructions of the boot ISA, the initial ISA instructions that the microprocessor fetches from architectural memory space after receiving a reset signal. The microprocessor also includes an execution pipeline, coupled to the hardware instruction translator. The execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.

Abstract: An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value on a lag select bus that indicates the propagation time. The adjust logic is coupled to a circuit and to the lag select bus, and adjusts the second value by an amount prescribed by the circuit to yield a third value that is output to an adjusted lag bus. The gray encoder gray encodes the third value to generate the first value on the lag bus.

Abstract: A power supply system for supplying power to a chipset of an electronic device is provided. The power supply system includes a voltage converter, converting a supply voltage of a power supply into a predetermined voltage and supplying the predetermined voltage to the chipset, and a power control circuit connected between the voltage converter and the power supply. The power control circuit further includes a switch and a switch controller. The switch has a first terminal connected to the power supply, a second terminal connected to the voltage converter and a control terminal The switch controller, connected to the control terminal of the switch and the chipset, controls the switch to couple the power supply to the voltage converter according to the turning-on of the power supply system.

Abstract: An identification technique for physically damaged blocks of a flash memory of a data storage device. In the data storage device, a controller coupled to the flash memory writes data into the flash memory with at least one time stamp corresponding to the data. The time stamp is taken into consideration by the controller to identify the physically damaged blocks of the flash memory, and thereby it is prevented from erroneously identifying a physically undamaged block as bad. Thus, the flash memory is prevented from being erroneously regarded as a write protected memory. The lifespan of the flash memory is effectively prolonged.

Abstract: Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores.