Abstract: A pin arrangement adapted to a FPC connector is provided. The pin arrangement includes a pin lane. The pin lane includes a pair of ground pins, a pair of differential pins and at least one not-connected (NC) pin. The differential pins are located between the pair of ground pins. The at least one NC pin is located between the pair of differential pins or between one of the pair of ground pins and one of the pair of differential pins adjacent thereto. By adding the at least one NC pin between the pair of differential pins and/or between the differential pin and the ground pin adjacent thereto, a distance between each of the pair of the differential pins and/or between the differential pin and the ground pin is increased, and thus a differential characteristic impedance of the pair of differential pins is raised to reduce the impact of impedance mismatch.

Abstract: A microprocessor includes functional units and control registers writeable to cause the functional units to institute actions that reduce the instructions-per-clock rate of the microprocessor to reduce power consumption when the microprocessor is operating in its lowest performance running state. Examples of the actions include in-order vs. out-of-order execution, serial vs. parallel cache access and single vs. multiple instruction issue, retire, translation and/or formatting per clock cycle. The actions may be instituted only if additional conditions exist, such as residing in the lowest performance running state for a minimum time, not running in a higher performance state for more than a maximum time, a user did not disable the feature, the microprocessor supports multiple running states and the operating system supports multiple running states.

Abstract: A circuit substrate includes a dielectric layer and a plurality of conductive structures. The dielectric layer has a plurality of conductive openings, a first surface, and a second surface opposite to the first surface. Each of the conductive openings connects the first surface and the second surface. The conductive openings are respectively filled with the conductive structures. Each of the conductive structures is integrally formed and includes a pad part, a connection part, and a protruding part. Each of the connection parts is connected to the corresponding pad part and the corresponding protruding part. Each of the protruding parts has a curved surface that protrudes from the second surface. A process for fabricating the circuit substrate is also provided.

Abstract: A system and a method for managing an expansion read-only memory (ROM), and a management host thereof are provided. The management host is connected with a computer host through a bridge. The management host establishes an address lookup table to assign a virtual function and an expansion ROM corresponding to the virtual function. When a request is issued by the computer host to obtain a size of the expansion ROM, the management host provides data in a shadow register block corresponding to the expansion ROM to the computer host according to the address lookup table. The computer host assigns a memory block in the computer host to the expansion ROM according to the data in the shadow register block. When a request is issued by the computer host to obtain data of the expansion ROM through the bridge, the management host provides the data of the expansion ROM to the computer host according to the memory block.

Abstract: A phase detecting apparatus and a phase adjusting method are provided. Determine whether to output a phase adjusting control signal according to a first data sampling value, a second data sampling value and a third data sampling value that are successively generated, so as to adjust a phase of a sampling clock signal used to sample a data signal.

Abstract: Methods for accessing hardware resources in an electronic device with a browser-based operating system (OS) which includes a user interface running in a browser are provided. A local server is first provided on the electronic device, wherein the local server has a corresponding URL and a dedicated network port. Then, upon receiving a service request from the client-side web application, the local server analyzes a service type of the service request and performs an operation to at least one of the hardware resources corresponding to the service type, wherein the service request is generated and directed to the local server according to the URL and the dedicated network port of the local server by the client-side web application on the electronic device.

Abstract: A chip package structure includes a carrier and a chip group. The chip group includes a pair of first chips that are identical IC chips. The pair of first chips are disposed on the carrier in opposite directions and parallel to each other, and electrically connected with the carrier.

Abstract: The invention discloses a computer system having voice-control function. The computer system includes a voice-recognition module, a shared memory, a microcontroller, a power-management module and a central processing unit. The voice-recognition module receives an external voice signal via a microphone and determines whether the external voice signal corresponds to an operation instruction. The shared memory is used for storing shared state information. The microcontroller is used for setting the shared state information according to the operation instruction when the external voice signal corresponds to the operation instruction. The power-management module generates a power-management signal according to the shared state information in the shared memory. When the power-management module transmits the power-management signal, the central processing unit executes a processing operation corresponding to the operation instruction according to the shared state information in the shared memory.

Abstract: An optical transceiver module coupled to a device is provided. The optical transceiver module includes an electronic signal transmitting terminal coupled to a receiving terminal of the device, an electronic signal receiving terminal coupled to a transmitting terminal of the device, an optical signal receiving terminal coupled to the electronic signal transmitting terminal, and an optical signal transmitting terminal coupled to the electronic signal receiving terminal. When the optical transceiver module is at an normal operation state and the electronic signal receiving terminal does not receive any electronic signal over a first predetermined time period, the optical transceiver module enters a idle detection state to make the electronic signal transmitting terminal to perform a receiver termination detection to the device to determine whether the device is coupled to the optical transceiver module.

Abstract: A power management method for use in an electronic system is provided. The electronic system has a processor and a power management unit. The method has the steps of: when the processor has entered a low power state and an awakening event occurs, calculating a staying time from the time point the processor enters the low power state till the time point the awakening event occurs, wherein the operation voltage of the processor is at a first voltage level in the low power state; and when the processing starts to exit the low power state according to the awakening event, determining a wait time, during which the operation voltage of the processor is recovered to a second voltage level of a working state from the first voltage level, wherein the first voltage level is lower than the second voltage level.

Abstract: A microprocessor instruction translator translates a conditional load instruction into at least two microinstructions. An out-of-order execution pipeline executes the microinstructions. To execute a first microinstruction, an execution unit receives source operands from the source registers of a register file and responsively generates a first result using the source operands. To execute a second the microinstruction, an execution unit receives a previous value of the destination register and the first result and responsively reads data from a memory location specified by the first result and provides a second result that is the data if a condition is satisfied and that is the previous destination register value if not. The previous value of the destination register comprises a result produced by execution of a microinstruction that is the most recent in-order previous writer of the destination register with respect to the second microinstruction.

Abstract: A microprocessor includes a plurality of memories each configured to hold microcode instructions. At least a first of the plurality of memories is configured to provide M-bit wide words of compressed microcode instructions, and at least a second of the plurality of memories is configured to provide N-bit wide words of uncompressed microcode instructions. M and N are integers greater than zero and N is greater than M. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the at least a first of the plurality of memories and before being executed.

Abstract: An apparatus including a BIOS read only memory (ROM) and a tamper detector. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest comprising an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is coupled to the BIOS ROM, and accesses the BIOS contents and the encrypted message digest upon reset of a microprocessor, and directs the microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the same algorithms and key that were employed to generate the first message digest and the encrypted message digest, and compares the second message digest with the decrypted message digest, and precludes the operation of the microprocessor if the second message digest and the decrypted message digest are not equal.

Abstract: A method for dynamically reconfiguring one or more cores of a multi-core microprocessor comprising a plurality of cores and sideband communication wires, extrinsic to a system bus connected to a chipset, which facilitate non-system-bus inter-core communications. At least some of the cores are operable to be reconfigurably designated with or without master credentials for purposes of structuring sideband-based inter-core communications. The method includes determining an initial configuration of cores of the microprocessor, which configuration designates at least one core, but not all of the cores, as a master core, and reconfiguring the cores according to a modified configuration, which modified configuration removes a master designation from a core initially so designated, and assigns a master designation to a core not initially so designated. Each core is configured to conditionally drive a sideband communication wire to which it is connected based upon its designation, or lack thereof, as a master core.

Abstract: A microprocessor includes one or more memories configured to hold microcode instructions, wherein at least a portion of the microcode instructions are compressed. The microprocessor also includes a decompression unit configured to decompress the compressed microcode instructions after being fetched from the one or more memories and before being executed. A method includes receiving from a memory a first N-bit wide microcode word, determining whether or not a predetermined portion of the first N-bit wide microcode word is a predetermined value, if the predetermined portion is not the predetermined value, decompressing the first N-bit wide microcode word to generate an M-bit wide microcode word, and if the predetermined portion is the predetermined value, receiving from the memory a second N-bit wide microcode word and joining portions of the first and second N-bit wide microcode words to generate the M-bit wide microcode word.

Abstract: A graphics display system is provided with a graphics processing module and a display module. The graphics processing module detects whether first frame data is equal to second frame data subsequent to the first frame data, and in response to the first frame data being equal to the second frame data, stops outputting any frame data after outputting the second frame data and a mode switching command. The display module displays graphic images according to the first frame data, and stores the second frame data as temporary data and continuingly displays the graphic images according to the temporary data in response to the mode switching command.

Abstract: A method for adjusting color values of a video signal. The video signal includes a first frame and a second frame prior to the first frame. The method includes steps of: determining a motion-level value of a first pixel in the first frame according to color values of the first pixel and a second pixel in the second frame; performing a first filtering operation to obtain an adjusted color value of the first pixel if the motion-level value is smaller than a first threshold; performing a second filtering operation to obtain the adjusted color value of the first pixel if the motion-level value is greater than a first threshold; and performing a third filtering operation to obtain the adjusted color value of the first pixel if the motion-level value lies between the first threshold and the second threshold.

Abstract: An interface chip capable of accurate link detection. The interface chip mounted on a first electronic device has a link layer and a physical layer. The link layer outputs data to be transformed and transmitted to a second electronic device by the physical layer. The data transmitted from the second electronic device is received and transformed by the physical layer and then conveyed to the link layer. The link layer includes a state machine, which performs a state modification on the first electronic device to rescue the second electronic device from a trapped state for confirming a link between the first and second electronic devices, wherein data output by the link layer and transformed and transmitted to the second electronic device by the physical layer is changed according to the state modification.

Abstract: PRD (Physical Region Descriptor) pre-fetch methods for DMA (Direct Memory Access) unit are provided. When a DMA out transaction for a memory is performed, it is determined whether a first queue is full or nearly full, wherein the first queue is used to store data corresponding to the DMA out transaction. If the first queue is full or nearly full, at least one PRD entry is read from a first PRD table, and stored to a first cache. When a DMA in transaction for the memory is performed, it is determined whether a second queue is empty or nearly empty, wherein the second queue is used to store data corresponding to the DMA in transaction. If the second queue is empty or nearly empty, at least one PRD entry is read from a second PRD table, and stored to a second cache.

Abstract: A through-hole layout structure is suitable for a circuit board. The through-hole layout structure includes a pair of first differential through-holes, a pair of second differential through-holes, a first ground through-hole, a second ground through-hole, and a third ground through-hole, which are all arranged on a first line. The first ground through-hole is located between the pair of first differential through-holes and the pair of second differential through-holes. The pair of first differential through-holes is located between the first ground through-hole and the second ground through-hole. The pair of second differential through-holes is located between the first ground through-hole and the third ground through-hole.