Abstract: A computer system is provided. In one embodiment, the computer system includes a memory, a peripheral device, a central processing unit (CPU), and a peripheral device controller. The CPU stores information about the data transmission in a descriptor in the memory when data transmission between the CPU and the peripheral device is required. The peripheral device controller reads the descriptor from the memory at an access frequency, records whether the descriptor read from the memory requests for data transmission as a recording result, and adjusts the access frequency according to the recording result.

Abstract: An apparatus including a ROM, a selector, and a detector. The ROM has partitions and encrypted digests. Each of the partitions is stored as plaintext, and each of the encrypted digests includes an encrypted version of a first digest associated with a corresponding one of the partitions. The selector selects one or more of the partitions responsive to an interrupt.

Abstract: An ISA-defined instruction includes an immediate field having a first and second portions specifying first and second values, which instructs the microprocessor to perform an operation using a constant value as one of its source operands. The constant value is the first value rotated/shifted by a number of bits based on the second value. An instruction translator translates the instruction into one or more microinstructions. An execution pipeline executes the microinstructions generated by the instruction translator. The instruction translator, rather than the execution pipeline, generates the constant value for the execution pipeline as a source operand of at least one of the microinstructions for execution by the execution pipeline.

Abstract: A duty cycle corrector includes a VCD (Voltage-Controlled Delay) circuit, an edge detector, an SR latch, a mode controller, and a CP (Charge Pump) circuit. The VCD circuit delays an input clock signal for a delay period so as to generate a delay clock signal. The delay period is adjusted according to a CP control voltage. The edge detector detects clock edges of the input clock signal and the delay clock signal so as to correspondingly generate a first clock edge signal and a second clock edge signal. The SR latch generates a toggling signal according to the first clock edge signal and the second clock edge signal. The mode controller generates a mode control voltage. The CP circuit operates in different modes according to the mode control voltage. The CP circuit generates the CP control voltage according to the toggling signal and the mode control voltage.

Abstract: A memory controller is provided. The memory controller includes a memory interface and an encoding module. The memory interface is configured to couple to a memory chip. The encoding module is coupled to the memory interface and includes a shared memory and a parity generation module. The parity generation module is coupled to the shared memory. The parity generation module reads at least one basic vector from the shared memory, determines a dimension of the at least one basic vector, generates a generation matrix according to the at least one basic vector, converts a raw data into a codeword through the generation matrix, and stores the codeword into the memory chip through the memory interface.

Abstract: A calibration method for an initial discharging curve of a battery is provided. The method includes: measuring a first open circuit voltage at a first time point, a corresponding first discharge capacity, a second open circuit voltage at a second time point, and a corresponding second discharge capacity according to an initial discharging curve; calculating an ideal discharge capacity according to the first discharge capacity and the second discharge capacity; measuring an real discharge capacity between the first time point and the second time point; determining a total discharge capacity difference according to the ideal discharge capacity and the real discharge capacity to calibrate the initial discharging curve to generate a current discharging curve.

Abstract: An electrostatic discharge protection device having a P-type substrate, a common N-well formed in the P-type substrate, a common N-doped region formed in the first common N-well, wherein the common N-doped region is electrically connected to a reference voltage node. The device further has a common P-doped region formed in the common N-well, wherein the common P-doped region surrounds the common N-doped region, the common P-doped region and the common N-well form a common diode, a plurality of peripheral N-wells formed in the P-type substrate and surrounding the common N-well, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and a circular P-doped region formed in the P-type substrate and disposed between the common N-well and the peripheral N-wells, and the circular P-doped region surrounding the common N-well.

Abstract: A rechargeable battery module including a plurality of battery cells connected in series, a charging transistor, a balancing circuit and a control chip. The charging transistor is operative to convey a charging current to charge the battery cells. Based on voltage levels of the battery cells, the control chip disables the charging transistor and controls the balancing circuit to perform a first stage battery balance process. After finishing the first stage battery balance process, the control chip enables the charging transistor to charge the battery cells again. After being switched to a constant voltage charging mode, the control chip controls the balancing circuit based on the voltage levels of the battery cells to perform a second stage battery balance process.

Abstract: An apparatus is provided for coupling a Universal Serial Bus (USB) device and a USB host. The apparatus includes a memory and a controller. The memory includes one or more descriptor entries. The controller is configured to obtain a descriptor of the USB device upon detection of the USB device on a USB bus, and compare the descriptor to a specific descriptor entry to generate a comparing result. Then the controller enables or disables a link path between the USB host and the USB device according the comparing result.

Abstract: Data checking and correction for a volatile memory of a data storage device, the data storage device further including a non-volatile memory and a controller. The controller operates the non-volatile memory in accordance with requests issued from a host. The controller uses the volatile memory for temporary storage of temporary data required for operations of the non-volatile memory. The controller generates error checking and correction content for the temporary data and writes the temporary data and the error checking and correction content into the volatile memory in at least one burst length for temporary storage of the temporary data. In this manner, it is not necessary to manufacture any additional pin on the volatile memory for data checking and correction.

Abstract: A computer system including telephone functionality. The computer system includes a first keyboard and a first display. The computer system also includes a processor having at least a first functional unit and a second functional unit, and further includes a phone portion. The computer system may operate in a first mode, a second mode, or a third mode. In the first mode, only the phone portion is activated, and the phone portion provides a functionality of placing and receiving phone calls without being removed from the computer system. In the second mode, the phone portion and first functional unit of the processor are activated. In the third mode, each of the phone portion, the first functional unit, and the second functional unit are activated.

Abstract: A first reticle set designed for manufacturing dies with a limited number of cores is modified into a second reticle set suitable for manufacturing at least some dies with at least twice as many cores. The first reticle set defines scribe lines to separate the originally defined dies. At least one scribe line is removed from pairs of adjacent but originally distinctly defined dies. Inter-core communication wires are defined to connect the adjacent cores, which are configured to enable the adjacent cores to communicate during operation without connecting to any physical input/output landing pads of the resulting more numerously cored die, which will not carry signals through the inter-core communication wires off the P-core die. The inter-core communication wires may be used for power management coordination purposes or to bypass the external processor bus.

Abstract: The present invention provides an electronic device including a write-once-then-read-only register, a chipset, a read-only memory, a flash memory and a central processor. The write-once-then-read-only register is arranged to store a determination value. The chipset is arranged to produce a CPU reset signal. The read-only memory is implemented in the chipset, and has a first memory block which corresponds to a predetermined address and is used to store a first instruction. The flash memory is coupled to the chipset, and has a second memory block which corresponds to the predetermined address and is used to store a second instruction. The central processor is arranged to determine the location of the predetermined address according to the CPU reset signal and the determination value.

Abstract: A microprocessor includes a cache memory and a control module. The control module makes the cache size zero and subsequently make it between zero and a full size of the cache, counts a number of evictions from the cache after making the size between zero and full and increase the size when the number of evictions reaches a predetermined number of evictions. Alternatively, a microprocessor includes: multiple cores, each having a first cache memory; a second cache memory shared by the cores; and a control module. The control module puts all the cores to sleep and makes the second cache size zero and receives a command to wakeup one of the cores. The control module counts a number of evictions from the first cache of the awakened core after receiving the command and makes the second cache size non-zero when the number of evictions reaches a predetermined number of evictions.

Abstract: A low-offset bandgap circuit including a core bandgap circuit and an offset-cancelling circuit is provided. The low-offset bandgap circuit provides a reference voltage at an output node. The core bandgap circuit includes a core operational amplifier to generate a core current. The offset-cancelling circuit is coupled to two input terminals of the core operational amplifier. The offset-cancelling circuit is configured to generate a compensation current according to the voltages at the two input terminals of the core operational amplifier so as to compensate for an offset voltage of the core operational amplifier. The reference voltage is generated according to the core current and the compensation current.

Abstract: A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state.

Abstract: The present disclosure provides systems and methods for compensating channel modulation effects. Some embodiments comprise a differential switching circuit, a common mode modulation circuit, and a current compensation circuit. The current compensation circuit compensates for channel modulation effects.

Abstract: A simple node transportation system having a vehicle traveling on a route having nodes, a traditional control module controlling the vehicle, and any combination of a node controller and a vehicle controller. The node controller has a traditional touch module connecting to the traditional control module and sending a control instruction to the traditional control module, an input module photographing an image and a gesture, a node control module recognizing the gesture and transferring the corresponding control instruction, and an output module displaying the image and the corresponding control instruction.

Abstract: A method of fabricating a circuit board includes the following steps. A first and a second patterned conductive layer are plated on the first and the second surface of a core substrate, respectively. A first and a second extending pad are individually plated on a first and a second pad of the first and the second patterned conductive layer, respectively. A first and a second thermal-curing type dielectric layer are individually formed on the first and the second surface to cover the first and the second patterned conductive layer and the first and the second extending pad, respectively. A portion of the first and the second thermal-curing type dielectric layer respectively covering the top of the first and the second extending pad are removed. A protective film covers the second extending pad. The extending pad is removed by an etching process.

Abstract: An intermediate electronic device, arranged to be coupled to a host system and an electronic device. The intermediate electronic device includes: a controller, enabled by an enable signal to process the data transmission between the host system and the electronic device; and a power transmission unit disposed between the host system and the electronic device. The power transmission units detect whether the power transmission unit is coupled to the host system or an external power source. When the power transmission unit detects that the power transmission unit is coupled to the host system, but not coupled to the external power source, the power transmission unit informs the host system to raise the voltage output to the intermediate electronic device to supply power to the electronic device, and outputs the enable signal.