Abstract: A microprocessor includes a branch target address cache (BTAC), each entry thereof configured to store branch prediction information for at most N branch instructions. An execution unit executes a branch instruction previously fetched in a fetch quantum. Update logic determines whether the BTAC is already storing information for N branch instructions within the fetch quantum (N is at least two), updates the BTAC for the branch instruction if the BTAC is not already storing information for N branch instructions, determines whether a type of the branch instruction has a higher replacement priority than a type of the N branch instructions if the BTAC is already storing information for N branch instructions, and updates the BTAC for the branch instruction if the type of the branch instruction has a higher replacement priority than the type of the N branch instructions already stored in the BTAC.

Abstract: A graphics pipeline configured to synchronize data processing according to signals and tokens has at least four components. The first component has one input and one output and communicates output tokens or wire signals after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The second component has one input and a plurality of outputs and communicates tokens or wire signals on one of the outputs after receiving tokens on the input, an internal event occurrence, or receipt of a signal on an input path. The third component has a plurality of inputs and one output and communicates tokens or wire signals on the output after receiving tokens on one of the inputs, an internal event occurrence, or receipt of a signal on an input path. The fourth component has a plurality of inputs and a plurality of outputs and has the capabilities of both the third and forth components.

Abstract: For determining a prediction mode parameter, a macroblock of an image is divided into a plurality of blocks; most prediction mode parameters corresponding to a plurality of first blocks along a left most edge of the macroblock are determined; most prediction mode parameters corresponding to a plurality of second blocks along a top most edge of the macroblock are determined; and the most prediction mode parameters of the first and second blocks are stored into a buffer allocated with designated position for the plurality of blocks.

Abstract: A differential signaling driver includes a current source, a differential signal generator, and a resistor. The current source is connected between an operation voltage and a first node, and supplies a driving current to the first node. The differential signal generator is connected between the first node and a second node. The differential signal generator receives a digital input signal, and generates a pair of differential output signals at a first output node and a second output node according to the digital input signal. The resistor is connected between the second node and a ground voltage. The differential signal generator couples the first output node to the operation voltage and the second output node to the ground voltage or couples the first output node to the ground voltage and the second output node to the operation voltage according to the digital input signal.

Abstract: An apparatus is provided for charging a Universal Serial Bus (USB) device according to an optimal charging mode. The apparatus includes a charging module that is configured to obtain a descriptor from the USB device upon detection of the USB device on a USB bus. The charging module includes one or more descriptor entries disposed in a memory and a controller. The one or more descriptor entries include descriptor data, for matching the descriptor to a specific descriptor entry, and charging data, that specifies the optimal charging mode for the USB device. The controller is coupled to the memory, and is configured to match the descriptor to the specific descriptor entry, and is configured to initiate the optimal charging mode on the USB bus according to the charging data.

Abstract: An apparatus including a microprocessor and a secure non-volatile memory. The microprocessor executes non-secure application programs and a secure application program. The non-secure application programs are accessed from a system memory via a system bus, and the secure application program is executed in a secure execution mode. The microprocessor has a watchdog manager that monitors environments of the microprocessor by noting and evaluating data communicated by a plurality of monitors, and that classifies the data to indicate a security level associated with execution of the secure application program, and that directs secure execution mode logic to perform responsive actions in accordance with the security level. The secure non-volatile memory is coupled to the microprocessor via a private bus, and stores the secure application program. The secure application program is encrypted.

Abstract: A memory management system and method include and use a cache buffer (such as a table look-aside buffer, TLB), a memory mapping table, a scratchpad cache, and a memory controller. The cache buffer is configured to store a plurality of data structures. The memory mapping table is configured to store a plurality of addresses of the data structures. The scratchpad cache is configured to store the base address of the data structures. The memory controller is configured to control reading and writing in the cache buffer and the scratchpad cache. The components are operable together under control of the memory controller to facilitate effective searching of the data structures in the memory management system.

Abstract: A non-volatile memory (NVM) apparatus and an operation method thereof are provided. A mapping table in a main memory is divided into a plurality of sub-mapping tables according to logical address groups. When an access command of a host is processed by the NVM apparatus, at least one corresponding sub-mapping table is selected from the sub-mapping tables according to a logical address of the access command. If the at least one corresponding sub-mapping table is required to be rebuilt, then the at least one corresponding sub-mapping table is rebuilt, and the logical address of the access command is converter for accessing the NVM apparatus according to the at least one corresponding sub-mapping table which has been rebuilt.

Abstract: An image processing apparatus and a method thereof are provided. A plurality of target blur radii are obtained by calculating blur radiuses corresponding to the out of focus transform function between a deblurred datum color channel image and the other color channel images. A plurality of deblurred color channel images are obtained by respectively performing deblurring operations on the original channel images according to the target blur radii that are corresponding to the original channel images. The deblurred datum color channel image and the deblurred color channel images are combined to obtain a blur calibrated image. Accordingly, the image out of focus problem induced by dispersion can be solved.

Abstract: A bridge is provided. The bridge is coupled between a host and a peripheral apparatus and includes a connector, a power circuit, and a bridge circuit. The connector connects the host and comprises a power pin. The power circuit converts a supplying power to a driving voltage when the power circuit is enabled. The bridge circuit is powered by the driving voltage and performs a data transmission procedure between the host and the peripheral apparatus. An enabling terminal of the power circuit is coupled to the power pin to receive an enabling signal transmitted by the host through the power pin. The power circuit is enabled to provide the driving voltage when the enabling signal is provided with a first potential. The power circuit is disabled to stop providing the driving voltage when the enabling signal is provided with a second potential.

Abstract: The present invention relates to a power management method for portable computers with a wireless device and detects the electric power source of a portable computer through a power source detection circuit during the operation of portable computer. In addition, any one of the following is dynamically changed: the supporting rate of the connection interface between a wireless device and the portable computer, the data rate between the AP (Access Point) and the wireless device. Moreover, the invention provides a plurality of input methods for triggering the power saving modes of the portable computer to achieve the object of reducing power consumption.

Abstract: A network-to-network bridge is provided. In one embodiment, the network-to-network bridge is coupled between a main system and a subsystem system. The main system includes a slot to couple with the subsystem, wherein the slot complies with the PCIe standard. The network-to-network bridge includes a transport layer and an internet layer but lacks of a network access layer allocated between the first main system and subsystem so as to transfer data by following the PCIe standard therebetween. The network-to-network bridge transfers data between the main system and the subsystem by accessing and employing their MAC addresses, and the network-to-network bridge can be allocated in the mainboard of the main system or the subsystem.

Abstract: A circuit board includes a substrate that has a top surface and a base surface opposite to each other, at least a top pad disposed on the top surface, a top solder resist layer disposed on the top surface and covering a portion of the top pad, and a pre-bump disposed on the top pad. The top solder resist layer has a first opening exposing a portion of the top pad. The pre-bump is located in the first opening and has a protrusion protruding from the top solder resist layer. A maximum width of the protrusion is less than or equal to a width of the top pad. A chip package structure having the circuit board is also provided.

Abstract: An apparatus including a microprocessor, a system memory, and a secure non-volatile memory. The microprocessor is mounted to a motherboard, and executes non-secure application programs and a secure application program. The system memory stores non-secure application programs, and is mounted to the motherboard and coupled to the microprocessor via a system bus. The microprocessor has secure execution mode logic that detects execution of a secure execution mode return event, and that terminates a secure execution mode within the microprocessor, where the secure execution mode exclusively supports execution of the secure application program. The secure non-volatile memory is coupled to the microprocessor via a private bus and stores the secure application program prior to termination of the secure execution mode, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.

Abstract: A microprocessor includes a model specific register (MSR) having an address, fuses manufactured with a first predetermined value, and a control register. The microprocessor initially loads the first predetermined value from fuses into the control register. The microprocessor also receives a second predetermined value into the control register from system software of a computer system comprising the microprocessor subsequent to initially loading the first predetermined value into the control register. The microprocessor prohibits access to the MSR by an instruction that provides a first password generated by encrypting a function of the first predetermined value and the MSR address with a secret key manufactured into the first instance of the microprocessor and enables access to the MSR by an instruction that provides a second password generated by encrypting the function of the second predetermined value and the MSR address with the secret key.

Abstract: A driving circuit is provided. The driving circuit is configured to generate an output signal according to an input signal generated from an input-stage voltage with a first voltage level and a reference voltage with a second voltage level. The driving circuit has a differential amplifier and an output stage. The differential amplifier has a first input terminal coupled to the reference voltage, a second input terminal coupled to the output signal, and an output terminal. The differential amplifier is supplied by an operation voltage with a third voltage level. The output stage is configured to receive the input signal and the operation voltage to generate the output signal. The second input terminal is coupled to the output terminal of the differential amplifier according to the input signal. The operation voltage is generated according to the input signal and the input-stage voltage.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a core clocks generator, and a synchronous strobe driver. The resistor network is configured to provide a ratio signal that indicates an amount to advance a synchronous data strobe associated with a data group. The core clocks generator is coupled to the ratio signal, and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.

Abstract: A multi-core processor includes microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process. In a related microcode-implemented method, states of a multi-core processor are discovered by at least two cores participating in a de-centralized inter-core state discovery process. The inter-core state discovery process is carried out through a combination of microcode executing on each participating core and signals exchanged between the cores through sideband non-system-bus communication wires. The discovery process is unmediated by any centralized non-core logic. Applicable discoverable states include target and composite power states, whether and how many cores are enabled, the availability and distribution of various resources, and hierarchical structures and coordination systems for the cores.

Abstract: An optical transceiver module adapted to a link device includes a connection unit, a driving unit and optical transmitting and receiving units. The connection unit, to be coupled with the link device, includes an indicating element for generating an indicating signal when the connection unit is coupled with the link device. The driving unit, coupled with the connection unit, receives the indicating signal and outputs a control signal according to the indicating signal. The optical transmitting unit, coupled with the driving unit, receives the control signal for driving the optical transmitting unit to output a first optical signal. The optical receiving unit, coupled with the driving unit, transmits a received second optical signal to the driving unit. An optical transmission device using the optical transceiver module, and an optical transmission method are also disclosed. A link training sequence can be initiated after the connection unit is actually coupled with the link device.

Abstract: An image processing system and an image processing method are provided. The image processing method includes following steps. Transformation matrixes between color channel images are obtained according to feature points in the color channel images. A transformation matrix having the minimum distortion is selected to determine a shift datum color channel image. The other color channel images are transformed according to the transformation matrixes corresponding to the shift datum color channel image. The shift datum color channel image and the transformed color channel images are combined to obtain a shift calibrated image. Thereby, the dispersion problem is resolved.