Abstract: An apparatus includes a fuse array, a random access memory (RAM), and a plurality of cores. The fuse array is disposed on a die, where the fuse array has a plurality of semiconductor fuses programmed with compressed configuration data. The RAM is disposed separately on the die. The plurality of cores is disposed separately on the die, where each of the plurality of cores is coupled to the fuse array and the RAM, and where the each of the plurality of cores accesses either the fuse array or the RAM upon power-up/reset as indicated by contents of a load data register to obtain the compressed configuration data.

Abstract: A system for integrating triangle setup and attribute setup operations into a programmable execution unit of a graphics processing unit is disclosed. A method for integrating triangle setup and attribute setup operations into a programmable execution unit graphics processing unit is also disclosed. In one embodiment, at least one execution unit is configured for multi-threaded operation. The at least one execution unit is configured to execute at least one thread for triangle setup operations and attribute setup operations as well as threads for pixel shader, geometry shader and vertex shader operations.

Abstract: An integrated circuit including a global supply bus, a gated supply bus, and a digital power gating system with controlled resume. The digital power gating system includes gating devices and a power gating control system. Each gating device has a pair of current terminals coupled between the global supply bus and the gated supply bus and each has a control terminal. The power gating control system controls a digital control value which controls activation of the gating devices. The power gating control system is configured to successively adjust the digital control value to increase a voltage of the gated supply bus from a reduced voltage level to a normal operating voltage level in response to a resume indication. The reduced voltage level may be a state retention level or full power gating. Successive adjustment may be with constant or adjusted gain using a constant clock or a dynamically adjusted clock.

Abstract: The present disclosure provides systems and methods for compensating channel modulation effects. Some embodiments comprise a differential switching circuit, a common mode modulation circuit, and a current compensation circuit. The current compensation circuit compensates for channel modulation effects.

Abstract: A battery control circuit for balancing a battery includes a voltage detector, a controller, a balancing device, and a switch. The voltage detector is configured to detect a voltage difference of the battery so as to generate a detecting signal. The controller is configured to generate a control signal according to the detecting signal. The switch is coupled between the battery and the balancing device, and is opened or closed according to the control signal, wherein if the voltage difference is greater than a threshold value, the switch is closed and the balancing device draws a load current from the battery, and if the voltage difference is smaller than or equal to the threshold value, the switch is opened and the balancing device is not capable of drawing any current.

Abstract: A signal generation device is provided to generate an output signal with constant frequency. The signal generation device includes a frequency-control circuit and a voltage-controlled delay line. The frequency-control circuit includes a pulse generator, generating a reference pulse signal according to a transition of the reference signal and a comparison pulse signal according to a transition of the comparison result signal, to re-shape the reference signal and the comparison result signal into narrow pulses suitable for clocking and resetting flip-flops.

Abstract: A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal).

Abstract: A transmission system receiving a first token packet and a second token packet is disclosed. The transmission system is coupled to a first peripheral device and a second peripheral device. The transmission system includes an upstream port to receive the first and the second token packets. A first transmission path occurs between the upstream port and the first peripheral device. A second transmission path occurs between the upstream port and the second peripheral device. The transmission system analyzes the first and the second token packets. The first token packet includes information corresponding to the first peripheral device. When the second token packet includes information corresponding to the first peripheral device, the transmission system disables the second transmission path.

Abstract: The invention provides a memory device. In one embodiment, the memory device comprises a flash memory, a memory, and a controller. The flash memory comprises a plurality of blocks for data storage. The memory stores an address mapping table recording relationships between logical addresses and physical addresses of the blocks therein. The controller divides the address mapping table stored in the memory to a plurality of mapping table units, updates relationships between the logical addresses and the physical addresses stored in the mapping table units, determines whether data access performed to the flash memory fulfills the conditions of a first specific requirement, and when the data access fulfills the conditions of the first requirement, the controller selects a target mapping table unit from the mapping table units, and stores the target mapping table unit and a corresponding time stamp as a mapping table unit data to the flash memory.

Abstract: A state machine circuit switching between multiple states is provided. The state machine circuit has: a state patch circuit for generating a patched predicted state value, a patched output value, and a selection signal according to a current state value and at least one of a second input signal, a predicted state value, and an output value of the state machine circuit; a first selection circuit for outputting the patched predicted state or the predicted state to a register according to the selection signal; and a second selection circuit for outputting the patched output value or the output value according to the selection signal, wherein the predicted state value and the output value are generated according to a first input signal and the current state value of the state machine circuit, and the predicted state value and the output value are not generated according to the second input signal.

Abstract: A microprocessor includes an input that receives an indication of the amount of instantaneous power being supplied to the microprocessor by an external power source. The microprocessor includes a plurality of processing cores that each receive the indication from the input and responsively determine an amount of energy consumed by the microprocessor during a preceding period. The period is a predetermined length of time. Each processing core operates at a frequency above a predetermined frequency in response to determining that the amount of energy consumed by the microprocessor during the preceding period is less than a predetermined amount of energy. The predetermined frequency may be: a frequency at which all the cores can operate over the predetermined length of time without the microprocessor consuming more than the predetermined amount of energy, or alternatively the maximum frequency at which system software may request the two or more processing cores to operate.

Abstract: The invention provides a mobile apparatus, adapted to communicate with a cloud server. The mobile apparatus includes a voice system, a communication module, and a processing unit. The processing unit is coupled to the communication module and the voice system. The communication module transmits the first voice signal to the cloud server. The cloud server parses the first voice signal to obtain a communication target and a communication instruction. The processing unit receives the communication target and searches an address book in the mobile apparatus according to the communication target for obtaining a selection list conforming with the communication target. When the voice system receives the second voice signal, the second voice signal and the selection list are transmitted to the cloud server simultaneously by the communication module for generating a selection target, and the processing unit receives and executes the communication instruction and the selection target.

Abstract: A region labeling method of data documents and a device thereof are provided. The region labeling method includes: obtaining a tree structure, which has a plurality of nodes including a plurality of administrative division names and iconic names with a hierarchical relationship therebetween; receiving the data document and retrieving at least one keyword from the data document; comparing the at least one keyword with the nodes to find a first node matching the at least one keyword; and labeling the first node and at least one father node of the first node to the data document.

Abstract: A sorting method of data documents is provided, adapted to an electronic device. The sort method includes the following steps: retrieving a plurality of keywords from contents of a plurality of data documents; retrieving corresponding keyword rankings of the plurality of keywords by a search engine; searching corresponding keyword categories of the plurality of keywords; and generating a sort algorithm based on the plurality of keywords, the keyword ranking and the keyword category of each of the plurality of keywords, and a current ranking of each of the plurality of data documents, wherein the sort algorithm is used to calculate a predicting ranking of another data document and to sort the another data document.

Abstract: A data transmission system and method are provided. The data transmission method receives a second format data packet sent by a host; decodes the second format data packet sent by the host, and translating the decoded second format data packet into a first format data packet; transmits the first format data packet to a first device; receives a transmission response sent by the first device in response to the first format data packet, determines whether to transmit the transmission response to the host, and performs a re-try flow when the transmission response does not need to be transmitted to the host. Preferably, a data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device, and the second format data packet is consistent with the second device.

Abstract: A scannable fast dynamic register including a data and scan enable circuit, a precharge circuit, a select circuit, a store circuit, and a scan input enable circuit. The data and scan enable circuit pulls a first precharge node to a discharge node in response to the clock upon evaluation in normal mode. The precharge circuit precharges first and second precharge nodes high, in which one of the precharged nodes discharges depending upon whether a data block evaluates. The store circuit and an output gate are responsive to the second precharge node to provide the output. The select circuit is interposed before the store circuit to allow injection of scan data in a scan mode. In scan mode, the scan input enable circuit provides scan data to the select and store circuits. The scan input enable circuit also includes a store circuit which operates with the first store circuit in a master-slave configuration.

Abstract: A core configuration discovery method and corresponding microprocessor are provided that does not rely on off-core logic or queries by system BIOS. Reset microcode is provided in the microprocessor's cores. Upon reset, the microcode queries and/or receives from other cores configuration-revealing information and collects the configuration-revealing information to determine a composite core configuration for the microprocessor. The composite core configuration may reveal the number of enabled cores, identify the enabled cores, reveal a hierarchical coordination system of the multi-core processor, such as a nodal map of the cores for certain inter-core communication processes or restricted activities, identify various domains and domain masters within such a system, and/or identify resources, such as voltage sources, clock sources, and caches, shared by various domains of the microprocessor. The composite core configuration may be used for power state management, reconfiguration, and other purposes.

Abstract: An out-of-order execution microprocessor for reducing the likelihood of having to replay a load instruction due to a store collision. The microprocessor includes a queue of entries, each entry configured to hold information that identifies sources of a store instruction used to compute its store address and to hold a dependency that identifies an instruction upon which the store instruction depends for its data. A register alias table (RAT), coupled to the queue of entries, is configured to encounter instructions in program order and to generate dependencies used to determine when the instructions may execute out of program order. In response to encountering a load instruction the RAT determines whether sources of the load instruction used to compute its load address match the sources of the store instruction in an entry of the queue, and if so, causes the load instruction to share the dependency of the matching store instruction.

Abstract: An architectural instruction instructs a microprocessor to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result, determines whether the architectural condition flags satisfy the condition, and updates a non-architectural indicator to indicate whether the architectural condition flags satisfy the condition.

Abstract: A display system and a display method for video walls are provided. The display system includes at least one server and a plurality of player devices. Each server renders an image and transmits the image to a network. The player devices are coupled to the at least one server through the network. Each player device receives the image or a part of the image rendered by one of the at least one server, and determines a synchronization time together with at least one of the other player devices. Each player device uses a display of a video wall to simultaneously display the image or the part of the image at the synchronization time.