Abstract: An image frame transmission method for use in a network transmission system is provided. The network transmission system includes an image sensor and an image processor. Firstly, a first image data segment of an image frame captured by the image sensor is outputted to the image processor in response to a first state of a control signal after an initial signal has been asserted by the image processor. Then, the output of a second image data segment of the image frame following the first image data segment to the image processor is delayed in response to the transition of the control signal from the first state to a second state. Afterward, the second image data segment is outputted to the image processor in response to the transition of the control signal from the second state to the first second state.

Abstract: An grouping bits interleaver includes a grouping bits unit and a data storage unit. The grouping bits unit is used for storing N data bits of an input data and outputting an address signal. Wherein each data bit is stored according to a bit position. The data storage unit coupled to the grouping bits unit is used for saving the content of the grouping bits according to the address signal. Compared to the conventional interleaver, the grouping bits interleaver has better memory usage, less access time, and smaller memory size.

Abstract: A computer system with integrated storage device for storing both a basic input/output system (BIOS) code and an operating system (OS) code and an associated booting method are provided. The computer system includes a central processing unit, a storage device controller and the storage device. The BIOS code and the OS code are stored in an invisible are and a visible area of the storage device, respectively. At first, the storage device controller is activated to read data from an architecture information area of the storage device to perform initialization. Then, the initialized storage device controller converts a read-only memory access command issued from the central processing unit into a suitable format to control loading of the BIOS code from the invisible area. At last, the storage device controller controls loading of the OS code from the visible area to finish the booting of the computer system.

Abstract: An apparatus with a dynamic interface protocol and a method for a dynamic interface protocol are provided. The apparatus is capable of consolidating multiple interface protocols to a single output terminal to reduce the number of output pins and the complexity and the cost of the apparatus. The apparatus is characterized by providing an output via the output terminal of the apparatus in accordance with a data protocol in a data mode, and providing the output via the output terminal in accordance with a video protocol in a video mode.

Abstract: A semiconductor chip including a substrate, a metal interconnection structure and a circuit region is provided. The substrate has at least one dielectric ring on a substrate surface of the substrate. The metal interconnection structure is disposed on the substrate surface and has at least one guard ring, wherein the guard ring comprises a plurality of individual segments, and the individual segments are individually and electrically coupled to the ground contacts. The circuit region disposed on the substrate. A projection of the dielectric ring on the substrate surface surrounds a projection of the circuit region on the substrate surface, and the projection of the guard ring on the substrate surface surrounds that of the dielectric ring and that of the circuit region on the substrate surface.

Abstract: A register circuit including a level shift circuit, a latch isolation circuit, and a keeper circuit for registering data with a lower voltage clock signal. The level shift circuit switches a level shift node between a reference voltage level and an upper voltage level in response to a clock node and an input node. The clock node toggles between the reference voltage level and a lower voltage level. The latch isolation circuit isolates an output node from the input node when the clock node is at the reference voltage level, and asserts the output node to one of the reference voltage level and an upper voltage level based on a state of the input node when the clock node is at the lower voltage level. The keeper circuit maintains a state of the output node when the clock node is at the reference voltage level.

Abstract: Application protection systems and methods. The system comprises a security platform device comprising a storage unit and a processing unit. The storage unit comprises a root security key and an application security key. The security platform device receives a unique key from an application. The processing unit encrypts the unique key using the root security key, and determines whether the encrypted unique key conforms to the application security key. If so, the application is allowed to execute.

Abstract: Various embodiments of shader processing systems and methods are disclosed. One method embodiment, among others, comprises a dependent texture read method executed using a multi-threaded, parallel computational core of a graphics processing unit (GPU). Such a method includes generating a dependent texture read request at logic configured to perform shader computations corresponding to a first thread, and sending shader-calculated, texture-sampling related parameters corresponding to the first thread to a texture pipeline while retaining at the logic all other shader processing related information corresponding to the first thread.

Abstract: A microprocessor that performs adaptive power throttling includes a calculation unit configured to calculate an average power consumed by the microprocessor over a most recent predetermined sample time and to determine whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The power management unit controls the microprocessor to operate at the predetermined frequency only if the microprocessor was most recently instructed by system software to operate at a highest frequency instructable by the system software. The highest frequency instructable by the system software is less than the predetermined frequency.

Abstract: An auto-focus method for camera is provided. First, a digital signal processor sets a first parameter p and a second parameter q. An image capture unit captures an only image. Then, the digital signal processor utilizes the only image, the first parameter p and the second parameter q to compute an object distance. Then, an optical focusing device utilizes the object distance to regulate a focal position. Therefore, the present invention substantially shortens the time for regulating the focal position.

Abstract: A computer system has a central processing unit, a north bridge electrically connected to the central processing unit, memory electrically connected to the north bridge, a south bridge electrically connected to the north bridge, and a peripheral device electrically connected to the south bridge. The south bridge includes a register for storings a plurality of pre-fetched read data to provide the pre-fetched read data to the peripheral device. The north bridge has an address queue module for storing an address of the pre-fetched read data, and a snooping module for checking whether a data value corresponding to the address is updated by the CPU. The north bridge assists the south bridge in obtaining and maintaining the pre-fetched read data for high efficiency and accuracy of read caching of the south bridge.

Abstract: An implement method of a FFT processor comprises the following steps. First, a 21 point FFT processor, which has an output and an input receiving a 2n+1 point data, is provided. A 2n-point FFT processor having an input and an output is provided. Sequentially, a multiplexer, which has a first input coupled to the output of the 21 point FFT processor, a second input receiving a 2n point data and an output coupled to the input of the 2n point FFT processor, is provided. When an input data is a 2n point data, the second input of multiplexer is coupled to the output thereof, and when an input data is a 2n+1 point data, the first input of multiplexer is coupled to the output thereof.

Abstract: A microprocessor includes a cache memory, a load unit, and a prefetch unit, coupled to the load unit. The load unit is configured to receive a load request that includes an indicator that the load request is loading a page table entry. The prefetch unit is configured to receive from the load unit a physical address of a first cache line that includes the page table entry specified by the load request. The prefetch unit is further configured to responsively generate a request to prefetch into the cache memory a second cache line. The second cache line is the next physically sequential cache line to the first cache line. In an alternate embodiment, the second cache line is the previous physically sequential cache line to the first cache line rather than the next physically sequential cache line to the first cache line.

Abstract: A method for determining the boundary strengths of edges in a block-based digitally encoded image is disclosed. The method includes setting the boundary strength of two adjacent blocks in an Inter macroblock to a first strength value if any one of the two adjacent blocks contains non-zero prediction residual in the encoding data and setting the boundary strength thereof to a second strength value if the two adjacent blocks are located in the same motion compensation block. An edge with boundary strength equal to the second strength value will be skipped in a deblocking process.

Abstract: The present invention is directed to a universal serial bus (USB) transaction translator and an associated IN isochronous transaction method. A device interface is coupled to a device via a device bus, and a host interface is coupled to a host via a host bus, wherein the host USB version is higher than the device USB version. At least two buffers configured to store data are disposed between the device interface and the host interface. A controller stores the data in the buffers alternately. A register is used to record device bus information. Before the host sends an IN packet, the controller pre-fetches data from the device according to the device bus information and then stores the data in the buffers; the controller responds with the pre-fetched data to the host after the host sends the IN packet.

Abstract: A PIP (Picture In Picture) processing apparatus processes a main image and a secondary image and includes a scaling circuit, a memory circuit, a first selecting circuit and a processing circuit. The scaling circuit scales down the secondary image to output a scaled-down secondary image. The memory circuit stores the main image and the scaled-down secondary image. The first selecting circuit is connected with a controlling circuit to receive an image selecting signal, and is connected with the memory circuit to select the scaled-down secondary image or the main image as an output according to the image selecting signal. The processing circuit is connected with the first selecting circuit to process the main image or the scaled-down image.

Abstract: A method for assisting multi-threaded command execution by a driver in a multi-core computer system, is disclosed. The method includes distinguishing asynchronous commands from synchronous commands, buffering the asynchronous commands in a buffer, processing the synchronous commands directly in a CPU driver thread, processing the asynchronous commands from the buffer by one or more CPU work threads, wherein multiple threads of the multi-core computer system can be utilized at the same time; and managing the buffer after the buffer is processed by the CPU work thread, wherein the command executions appear to be just like single-threaded to application software.

Abstract: A microprocessor includes a memory that stores instructions of a non-user program to implement a user program instruction of the user-visible instruction set of the microprocessor. The non-user program includes a conditional branch instruction. A first fetch unit fetches instructions of the user program that includes the instruction that is implemented by the non-user program. An instruction decoder decodes the user program instructions and saves a state in response to decoding the user program instruction that is implemented by the non-user program. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the non-user program other than the conditional branch instruction. A second fetch unit fetches the non-user program instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.

Abstract: The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. In one embodiment a method for graphics processing comprises assigning at least one execution unit to each of a plurality of shader units, the plurality of shader units comprising a vertex shader, a geometry shader, and a pixel shader, wherein an execution unit assigned to a given shader unit performs processing tasks for only that shader unit, determining that one of the plurality of shader units is bottlenecked, and reassigning at least one execution unit from a non-bottlenecked shader unit to the shader unit determined to be bottlenecked.

Abstract: Disclosed are systems and methods for debugging and analyzing graphics hardware designs. Hardware designs are represented by a software model implemented in a programming language. Graphics operations can be executed in the software model as well as in reference software models to allow a user to analyze the accuracy of a graphics hardware design and/or a device driver implementation.