Patents Assigned to VIA Technologies
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Patent number: 8013649Abstract: A dynamic clock feedback latch includes a feedback path that generates a data value on an output as a function of data inputs in response to a clock input going low and generates a latching value on the output after a delay from the clock input going high. A first transistor pre-charges a node high while the clock input is low. A second transistor provides a drain path for draining the node low from the pre-charged value while the clock input is high. The output controls a third transistor during the delay to drain the node to a low value if the data value is high and to retain the high value if the data value is low. The feedback path generates the predetermined latching value on the output after the delay to cause an inverted value of the data value to be latched onto the node.Type: GrantFiled: October 7, 2009Date of Patent: September 6, 2011Assignee: VIA Technologies, Inc.Inventor: John L. Duncan
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Patent number: 8014440Abstract: A frequency adjusting method of a CDR circuit and apparatus thereof are provided. The adjusting method is applied to a receiver apparatus connected to an outer apparatus. The outer apparatus, after actuated, sends out an outer data signal to the receiver apparatus according to its operational frequency and a PLL of the receiver apparatus outputs a transmitter clock according to an operational frequency of the receiver apparatus. The CDR circuit of the receiver apparatus generates a receiver clock according to the outer data signal. The CDR circuit is set in a phase mode such that the receiver clock follows transmitting frequency of the outer data signal. Then, a difference between frequencies of the receiver clock and the transmitter clock is checked. If the difference is larger than a threshold value, an operational frequency of the outer data signal is reduced.Type: GrantFiled: March 2, 2007Date of Patent: September 6, 2011Assignee: VIA Technologies, Inc.Inventor: Chin-Fa Hsiao
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Patent number: 8010775Abstract: A method for reducing computer system power consumption. The computer system includes a memory module having a plurality of address pins, and a chipset having a plurality of driving units for driving the address pins. The method includes obtaining number of required address pins by detecting a capacity of the memory module, and disabling the driving units so as to make a number of the active driving units substantially equal to the number of the required address pins.Type: GrantFiled: October 15, 2008Date of Patent: August 30, 2011Assignee: VIA Technologies Inc.Inventor: Jiing Lin
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Patent number: 8004531Abstract: Multiple graphics processor system and method embodiments are disclosed. One system embodiment, among others, comprises a multiple graphics processor system, comprising a first graphics processing unit having first status information and a second graphics processing unit having second status information, and first key logic corresponding to the first graphics processing unit, the first key logic configured to compare the first and second status information and communicate to the first graphics processing unit a key corresponding to the lowest completed stage of processing among the first and second graphics processing units.Type: GrantFiled: October 13, 2006Date of Patent: August 23, 2011Assignee: Via Technologies, Inc.Inventors: Wen-Chung Chen, Li Liang, Shou-Yu Joyce Cheng, Dehai (Roy) Kong, Mitch Singer
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Patent number: 8006014Abstract: A PCI-Express data link transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one of multiple scheduled TLPs and DLLPs based on their distinct types. A selector selects one of the arbiters to select the one of the multiple scheduled TLPs and DLLPs for transmission. A programmable storage element provides a value to control the selector. In one embodiment, the distinct priority rule employed by at least a first of the arbiters prioritizes TLPs higher than Ack/Nak DLLPs, and the distinct priority rule employed by at least a second of the arbiters prioritizes Ack/Nak DLLPs higher than TLPs. In one embodiment, at least a first arbiter prioritizes TLPs higher than Ack/Nak DLLPs and UpdateFC DLLPs, at least a second arbiter prioritizes Ack/Nak DLLPs higher than TLPs and UpdateFC DLLPs, and at least a third arbiter prioritizes UpdateFC DLLPs higher than TLPs and Ack/Nak DLLPs.Type: GrantFiled: July 24, 2009Date of Patent: August 23, 2011Assignee: VIA Technologies, Inc.Inventors: Yen-Ting Lai, Wen-Yu Tseng
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Patent number: 8005318Abstract: A weight-adjusted method applied in adjusting a weighting coefficient in an image scaling process. First, an absolute difference is obtained by taking an absolute value of a difference between a first pixel value and a second pixel value of an image. Next, the absolute difference is compared with several threshold values, which define several zones, so as to generate a weight-adjusted value corresponding to a zone in which the absolute difference falls. After that, a first pixel weighted value and a second pixel weighted value are adjusted according to the weight-adjusted value. Finally, a weighted pixel value is outputted by adding a product of the first pixel value and a first adjusted pixel weighted value to a product of the second pixel value and a second adjusted pixel weighted value.Type: GrantFiled: June 18, 2007Date of Patent: August 23, 2011Assignee: Via Technologies, Inc.Inventors: Tse-Hua Ou, Sheng-Che Tsao
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Patent number: 8004533Abstract: A command parser in a GPU is configured to schedule execution of received commands and includes a first input coupled to a scheduler. The first command parser input is configured to communicate bus interface commands to the command parser for execution. A second command parser input is coupled to a controller that receives ring buffer commands from the scheduler in association with a new or previously-partially executed ring buffer, or context, which are executed by the command parser. A third command parser input coupled to a command DMA component that receives DMA commands from the controller that are also contained in the new or previously-partially executed ring buffer, which are forwarded to the command parser for execution. The command parser forwards data corresponding to commands received on one or more the first, second, and third inputs via one or more outputs.Type: GrantFiled: September 8, 2006Date of Patent: August 23, 2011Assignee: VIA Technologies, Inc.Inventors: Hsilin Huang, Boris Prokopenko, John Brothers
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Publication number: 20110202775Abstract: A method for performing a hash operation, including providing an atomic hash instruction that directs a microprocessor to perform a the hash operation and to indicate whether the hash operation has been interrupted by an interrupting event; translating the atomic hash instruction into first and second micro instructions; via a hash unit, first executing the first micro instructions to accomplish the hash operation according to the hash mode; and via an integer unit, second executing the second micro instructions in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation. The atomic hash instruction has an opcode field, configured to prescribe the hash operation, and a hash mode field, configured to prescribe that the microprocessor accomplish the hash operation according to a one of a plurality of hash modes.Type: ApplicationFiled: January 20, 2011Publication date: August 18, 2011Applicant: VIA Technologies, Inc.Inventors: Thomas A. Crispin, G. Glenn Henry, Terry Parks
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Patent number: 8000191Abstract: A method reads text data from a musical disc in a disc drive. The musical disc includes a plurality of blocks each including a plurality of packs. Each pack is given a block number and a sequence number and written to a ring buffer of a disc drive including a first memory and a second memory.Type: GrantFiled: January 11, 2006Date of Patent: August 16, 2011Assignee: Via Technologies, Inc.Inventor: Chun-Lung Liu
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Patent number: 7999819Abstract: Provided are methods for managing texture data. The methods include preloading a first plurality of texture descriptor values from a memory location in a first buffer located in a first logic block, wherein the first buffer is further configured to receive data corresponding to non-texture functions performed in the first logic block and preloading the first plurality of texture descriptor values from a memory location into a second buffer in a second logic block if the first buffer is full. The methods further include utilizing the first plurality of texture descriptor values, within the second logic block, to perform a shader calculation, and loading, dynamically, a second plurality of texture descriptor values from memory into the first buffer, wherein the first logic block requires additional data. Additionally, the methods can include writing, if the first buffer is full, the second plurality of texture descriptor values over a portion of the first plurality of texture descriptor values.Type: GrantFiled: November 20, 2007Date of Patent: August 16, 2011Assignee: Via Technologies, Inc.Inventors: Fred Liao, Yijung Su, Yiping Chen, Mark Zheng
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Patent number: 7996650Abstract: A microprocessor performs a speculative page tablewalk. The microprocessor includes a tablewalk engine that determines whether at least one of a predetermined set of conditions exists with respect to characteristics of the page of memory whose physical address specified by a memory access instruction is missing in the TLB, performs operations of the tablewalk in an out-of-order manner with respect to the execution of unretired program instructions older than the memory access instruction while none of the predetermined set of conditions exists, and waits to perform the operations of the tablewalk until the microprocessor has retired all program instructions older than the memory access instruction when at least one of the predetermined set of conditions exists. The predetermined set of conditions may include the tablewalk needing to load information from a strongly-ordered page, update page mapping information, or access a global page.Type: GrantFiled: July 14, 2008Date of Patent: August 9, 2011Assignee: VIA Technologies, Inc.Inventors: Colin Eddy, Rodney E. Hooker
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Patent number: 7996586Abstract: A USB port transmitter includes a plurality of arbiters, each employing a distinct priority rule to select one USB transmission from among multiple scheduled USB transmissions based on their types. A selector selects one of the arbiters to select the one USB transmission from among the multiple scheduled USB transmissions. A programmable storage element controls the selector to select the one arbiter. In one embodiment, at least a first arbiter prioritizes header/data packets higher than link commands, and at least a second arbiter prioritizes link commands higher than header/data packets. In one embodiment, at least one arbiter prioritizes flow control and power management link commands higher than header/data packets. In one embodiment, at least a first of the arbiters prioritizes USB LGO_Ux link commands higher than USB LAU/LXU link commands, and at least a second arbiter prioritizes USB LAU/LXU link commands higher than USB LGO_Ux link commands.Type: GrantFiled: July 24, 2009Date of Patent: August 9, 2011Assignee: VIA Technologies, Inc.Inventor: Meng-Fang Liu
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Patent number: 7990180Abstract: A fast dynamic register circuit including first and second precharge circuits, a keeper circuit and an output circuit. The first and second precharge circuits each precharge a corresponding one of a pair of precharge nodes and cooperate to minimize setup and hold times. If an input data node is low when the clock goes high, the first precharge node remains high causing the second precharge node to be discharged. Otherwise if the input node is high, the first precharge node is discharged and the second remains charged. Once either precharge node is discharged, the output state of the register remains fixed until the next rising clock edge independent of changes of the input data node. The fast dynamic register may be implemented with multiple inputs to perform common logic operations, such as OR, NOR, AND and NAND logic operations.Type: GrantFiled: September 9, 2009Date of Patent: August 2, 2011Assignee: VIA Technologies, Inc.Inventors: James R. Lundberg, Imran Qureshi
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Patent number: 7991924Abstract: A system for a first device to initialize a second device is disclosed. The initialization bus is coupled between the first device and the second device. During an initialization period, the first device triggers at least one transmission command through the initialization bus to transmit at least one initial value to the second device via the initialization bus.Type: GrantFiled: December 14, 2006Date of Patent: August 2, 2011Assignee: Via Technologies, Inc.Inventors: Chun-Yuan Su, I-Lin Hsieh, Chi-Feng Lin
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Patent number: 7990181Abstract: A clockless return to state domino logic gate is disclosed responsive to multiple input nodes including at least one return to state node. A domino circuit presets a preset node to a second state. The domino circuit switches to a latch state and switches an output node when the preset node is pulled to a first state, and resets back to the preset state and switches the output node back to its default state when a reset node is pulled to the second state. An evaluation circuit pulls the preset node to the second state when the input nodes are in an evaluation state. An enable circuit enables a reset condition when the domino circuit is in its latch state. A reset circuit pulls the reset node to the first state after an evaluation event when the input nodes are no longer in the evaluation state.Type: GrantFiled: July 20, 2010Date of Patent: August 2, 2011Assignee: VIA Technologies, Inc.Inventor: Daniel F. Weigl
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Patent number: 7991990Abstract: A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly.Type: GrantFiled: December 14, 2007Date of Patent: August 2, 2011Assignee: VIA Technologies, Inc.Inventors: Chien-Ping Chung, Lin-Hung Chen
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Patent number: 7987312Abstract: A method for dynamically determining bit configuration for a host bridge. The method first obtains information of peripheral components coupled to the host bridge. Next, the method dynamically determines a bit configuration of a processor system bus connecting to the host bridge according to the obtained information.Type: GrantFiled: July 30, 2004Date of Patent: July 26, 2011Assignee: Via Technologies, Inc.Inventors: Robert Shih, Jing-Rung Wang
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Patent number: 7987408Abstract: In a data processing and buffering method, at least one read cycles are asserted to obtain at least one data, respectively, wherein each of the data includes at least one sub data and each data is specified with an address pointer and an enable bit array. When a certain sub data is received, the corresponding bit of the enable bit array is enabled. The corresponding sub data of the enabled bit is indicated by the address pointer.Type: GrantFiled: October 17, 2006Date of Patent: July 26, 2011Assignee: Via Technologies, Inc.Inventor: Chun-Yuan Su
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Patent number: 7986036Abstract: An arrangement scheme for a power/ground (P/G) network of an integrated circuit is provided. Rows of standard cells in the integrated circuit are horizontally arranged. The P/G network has horizontal and vertical metal lines arranged in different metal layers. The horizontal metal lines have horizontal power metal lines and horizontal ground lines. The vertical metal lines have vertical power metal lines and vertical ground lines. The power lines and the ground lines in the horizontal metal lines are respectively interconnected with the power lines and the ground lines of the vertical metal lines. The width of the horizontal metal wires in the P/G network is such that the horizontal power metal lines only cover the power lines in the rows of the standard cells, while the horizontal ground metal lines only cover the ground lines of the rows of the standard cells.Type: GrantFiled: August 6, 2007Date of Patent: July 26, 2011Assignee: VIA Technologies, Inc.Inventor: Xiaoshan Chen
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Patent number: 7978001Abstract: A microprocessor according to one embodiment includes a supply node providing a core voltage, a functional block, a charge node, select logic, and substrate bias logic. The functional block has multiple power modes and includes one or more semiconductor devices and a substrate bias rail routed within the functional block and coupled to a substrate connection of at least one semiconductor device. The select logic couples the substrate bias rail to the charge node when the functional block is in a low power mode and clamps the substrate bias rail to the supply node when the functional block is in a full power mode. The substrate bias logic charges the charge node to a bias voltage at an offset voltage relative to the core voltage when the functional block is in the low power mode. Semiconductor devices may be provided to clamp or otherwise couple the bias rail.Type: GrantFiled: September 25, 2008Date of Patent: July 12, 2011Assignee: VIA Technologies, Inc.Inventors: Raymond A. Bertram, Mark J. Brazell, Vanessa S. Canac, Darius D. Gaskins, James R. Lundberg, Matthew Russell Nixon