Abstract: A multi-core/multi-package bus termination apparatus includes a configuration array and a plurality of drivers. The configuration array generates location/protocol signals that each direct one of the plurality of drivers on the bus to employ location-based bus termination or protocol-based bus termination. The plurality of drivers is coupled to the plurality of location/protocol signals, a plurality of location signals, a bus ownership signal, and a multi-package signal. Each of the plurality of drivers controls how one of a plurality of nodes is driven responsive to a first state of one of the plurality of location/protocol signals.

Abstract: A leadframe for a leadframe type package includes a chip base, and leads constituting lead lanes. One lead lane includes a pair of first differential signal leads, a pair of second differential signal leads, a pair of third differential signal leads between which and the pair of first differential signal leads is arranged the pair of second differential signal leads, a first power lead arranged between the pair of first and second differential signal leads, a second power lead arranged between the pair of second and third differential signal leads, and a third power lead between which and the second power lead is the pair of third differential signal leads. A voltage provided by the first power lead is less than a voltage provided by the second power lead, and the voltage provided by the second power lead is substantially equal to a voltage provided by the third power lead.

Abstract: An electric assembly includes a circuit board and an electric connector. The circuit board comprises a first surface and a second surface opposite thereto. The electric connector includes a metallic case, an insulating base, first leads and second leads. The insulating base is connected with the metallic case. The first leads are disposed on the insulating base and soldered to the first surface. The first leads includes a pair of first differential signal leads, a pair of second differential signal leads and a ground lead located between the pair of first differential signal leads and the pair of second differential signal leads. The second leads are disposed on the insulating base and soldered to the second surface. The second leads include a power lead, a second ground lead and a pair of third differential signal leads located between the power lead and the second ground lead.

Abstract: A program instruction rearrangement method calculates the dependency depth of each instruction of a program based on dependency between instructions, based on register access order, and rearranging instructions based on the dependency depth. Additionally, the dependency between instructions can be utilized to locate and remove redundant instructions.

Abstract: Included are systems and methods for supporting a plurality of Graphics Processing Units (GPUs). At least one embodiment of a system includes a context status register configured to send data related to a status of at least one context and a context switch configuration register configured to send instructions related to at least one event for the at least one context. At least one embodiment of a system includes a context status management component coupled to the context status register and the context switch configuration register.

Abstract: A spiral inductor is provided. The spiral inductor includes a first spiral conductive trace with at least one turn, a second spiral conductive trace, and a connector. The first spiral conductive trace comprises an outer end and an inner end. The second spiral conductive trace surrounds a portion of the outermost turn of the first spiral conductive trace, and comprises a first end and a second end. The connector electrically connects to the inner end and the first end.

Abstract: Methods, devices, and systems for charging a battery in a mobile device are provided. For example, in one embodiment, among others, a battery charging system includes a monitoring circuit configured to monitor a battery and generate a sense current. The battery charging system further includes a comparing circuit configured to compare a reference current and the generated sense current. The comparing circuit is further configured to generate a comparison signal. Also, the battery charging system further includes a control circuit configured to control a level of a charging current applied to the battery based on the comparison signal.

Abstract: A host module is disclosed, in which an interface is used to couple to at least an electronic device through a serial bus and comprises at least first and second ports. A detection unit reports that one of the first and second ports is enabled and the other is not enabled to a serial bus host driver and enables the interface to perform data transmission with the electronic device connected to the first and second ports through two parallel transmission channels of the serial bus, when the first and second ports are both connected to the same electronic device through the serial bus.

Abstract: A request scheduling method is provided in a request accessing system having a processing unit, an upstream unit coupled to the processing unit, a downstream unit coupled to the processing unit and the upstream unit, and at least one endpoint device coupled to the upstream unit and the downstream unit, wherein the endpoint device asserts at least one request to the upstream unit. The request scheduling method includes: transmitting the request to a processing unit while the request is a non-peer-to-peer request, and transmitting the request to a downstream unit while the request is a peer-to-peer request; wherein if the request is a peer-to-peer and posted request and there is a previous asserted request which is peer-to-peer and non-posted request and the previous asserted request has a latency exceeds a predetermined time, transmitting the request earlier than the previous asserted request to the downstream unit.

Abstract: Included are embodiments of a description language program stored in a computing device for updating a first version of a computer program. In at least one embodiment, the first version of the computer program is written in a universal format and the program includes logic configured to receive an updated version of the computer program. Other embodiments include logic configured to retrieve the first version of the computer program and logic configured to translate the updated version of the computer program from a proprietary format to the universal format. Still other embodiments include logic configured to utilize at least one tag to compare the translated updated version of the computer program with the first version of the computer program.

Abstract: A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued. A retire unit makes a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result.

Abstract: A microprocessor instruction translator translates a macroinstruction into three microinstructions to perform a read/modify/write operation on a memory operand. A first microinstruction instructs the microprocessor to calculate a source address and to load the memory operand into the microprocessor from memory at the source address and to calculate a destination address. The second microinstruction instructs the microprocessor to perform an arithmetic or logical operation on the loaded memory operand to generate a result. The third microinstruction instructs the microprocessor to write the result to memory at the destination address calculated by the first microinstruction. A first execution unit receives the first microinstruction and responsively calculates the source address and loads the memory operand into the microprocessor from memory at the source address. A second execution unit also receives the first microinstruction and calculates the destination address.

Abstract: The present disclosure provides embodiments of guard band clipping systems and methods. One guard band clipping system embodiment, among others, includes a vertex processor configured to convert transformed vertex data to integer screen space data and pass the transformed vertex data downstream in a graphics hardware pipeline, and a guard band clipping module coupled to the vertex processor and a guard band arithmetic logic unit coupled to the guard band clipping module, the guard band clipping module configured to determine whether a primitive corresponding to the transformed vertex data is to be clipped and, based on that determination, forward the primitive to the guard band arithmetic logic unit to perform guard band clipping.

Abstract: A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first instruction includes a field for indicating whether to update the plurality of condition code flags of the architectural or non-architectural register. A second instruction of the microarchitectural instruction set instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags. The second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the architectural or non-architectural register to determine whether to perform the operation.

Abstract: The invention provides a method for buffering output pixel data of a Joint Photographic Experts Group (JPEG) image. First, a storing rule is determined for storing a scaled minimum coded unit (MCU) of the JPEG image in a memory module, wherein the scaled MCU comprises a plurality of pixels. A memory is then selected from the memory module according to the storing rule for storing pixels of the scaled MCU. Finally, the pixels of the scaled MCU are then output from the memory module to a frame buffer.

Abstract: The present invention is directed to de-interlacing method and apparatus using remote interpolation. An up window and a down window are firstly determined. The closest pair of pixels of the up window and the down window along a direction of 90°, ?45°, and 45° is determined, which is then used to interpolate a new pixel. Subsequently, the up window and the down window are moved or stayed according to which pair is determined as being closest.

Abstract: Provided is a control method for an advanced configuration and power interface (ACPI) in a computer system. The computer system comprises a processor and a bus master, wherein the processor, as defined by the ACPI specification, has a first state (C0 state), a second state (C1 state), a third state (C2 state), a fourth state (C3 state) and a fifth state (C4 state). The method comprises enabling the processor to run in the C2 state when a request from the bus master is issued before the processor enters the C3 state, or enables the processor to ignore the C4 state and complete the C3 state when the request from the bus master is issued at the C3 state and before entering the C4 state.

Abstract: A method for playing DVD. A method for simultaneously outputting a DVD movie to multiple channels each having its own playback parameters such as view angle, spoken language and subtitle language, using a single DVD player.

Abstract: An apparatus and method for performing cryptographic operations within microprocessor. The apparatus includes an instruction register having a cryptographic instruction disposed therein, a keygen unit, and an execution unit. The cryptographic instruction is received by a microprocessor as part of an instruction flow executing on the microprocessor. The cryptographic instruction prescribes one of the cryptographic operations, and also prescribes that a user-generated key schedule be employed when executing the one of the cryptographic operations. The keygen unit is operatively coupled to the instruction register. The keygen unit directs the microprocessor to load the user-generated key schedule. The execution unit is operatively coupled to the keygen unit. The execution unit employs the user-generated key schedule to execute the one of the cryptographic operations. The execution unit includes a cryptography unit.

Abstract: The present invention provides a method of hot switching data transfer rate on the bus to hot switch the data transfer rate of the bus between the control chips without the process of RESET. When the bus between the control chips demands a large amount of data transfer, the bus is hot switched to a higher data transfer rate to fulfill the data transfer requirement. Contrarily, when the bus between the control chips demands less amount of data transfer, the bus is hot switched to a lower data transfer rate to save power consumption.