Abstract: A microprocessor that performs adaptive power throttling includes a calculation unit that calculates an average power consumed by the microprocessor over a most recent predetermined sample time and determines whether the average power is less than a predetermined maximum power value. A power management unit controls the microprocessor to conditionally operate at a predetermined frequency if the average power is less than the predetermined maximum power value. The predetermined frequency is a frequency at which the microprocessor may consume more than the predetermined maximum power value. The predetermined maximum power value and sample time are specified to achieve power and/or thermal design goals of a system in which the microprocessor operates. The predetermined maximum power and/or sample time values are programmable by system software.

Abstract: A device for protecting a PLL in reading signals on a defect disc from disturbance and instability is provided. The device includes a defect detection unit, a logic combination unit and a PLL. The defect detection unit receives a plurality of defect detection signals to detect various defects for setting a plurality of defect flag signals, wherein the plurality of defect detection signals include at least an envelope of RF signal and bit modulation signals. The logic combination unit performs logic operation on the defect flag signals in order to detect a specified defect. Wherein, when the specified defect is detected, the PLL uses different bandwidths to compensate a digitalized RF signal affected by the specified defect. A method for protecting a PLL in reading signals on a defect disc is also provided.

Abstract: A multi-processor system and a dynamic power saving method thereof are provided. The multi-processor system includes a plurality of processors and a chipset. Each of the processors has a plurality of standard bus request pins and a specific bus request pin, and the standard bus request pins of each processor are alternately connected to the standard bus request pins of other processors respectively. The chipset is coupled to the specific bus request pins of the processors for detecting a control request signal on the specific bus request pins. When the chipset detects the control request signal, the chipset turns on an input buffer connected with the processors so that the processors can access data through the input buffer. When the chipset does not detect the control request signal, the chipset turns off the input buffer.

Abstract: A method for performing hash operations including: receiving a hash instruction that prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit, executing the one of the hash operations. The executing includes indicating whether the one of the hash operations has been interrupted by an interrupting event; first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.

Abstract: A method for performing hash operations including: receiving a hash instruction that is part of an application program, where the hash instruction prescribes one of the hash operations and one of a plurality of hash algorithms; translating the hash instruction into a first plurality of micro instructions and a second plurality of micro instructions; and via a hash unit disposed within execution logic, executing the one of the hash operations. The executing includes first executing the first plurality of micro instructions within the hash unit to produce output data; second executing the second plurality of micro instructions within an x86 integer unit in parallel with the first executing to test a bit in a flags register, to update text pointer registers, and to process interrupts during execution of the hash operation; and storing a corresponding intermediate hash value to memory prior to allowing a pending interrupt to proceed.

Abstract: A microprocessor includes a control register that stores a control value that affects operation of the microprocessor. An instruction set architecture includes a conditional branch instruction that specifies a branch condition based on the control value stored in the control register, and a serializing instruction that updates the control value in the control register. The microprocessor completes all modifications to flags, registers, and memory by instructions previous to the serializing instruction and to drain all buffered writes to memory before it fetches and executes the next instruction after the serializing instruction. Execution units update the control value in the control register in response to the serializing instruction. A fetch unit fetches, decodes, and unconditionally correctly resolves and retires the conditional branch instruction based on the control value stored in the control register rather than dispatching the conditional branch instruction to the execution units to be resolved.

Abstract: A method for prefetching data in a bus system is provided. First, according to an address signal from a master, a prefetching address generator generates a prefetching address signal and transfers it to a first select circuit. In response to a signal from the master indicates that the address is related to the previous address and the control signal is identical to the previous transfer, or in response to a signal from the master indicates that the address and control signals are unrelated to the previous transfer but is matched to a hit logic, a prefetching controller directs the first select circuit to transfer the prefetching address signal to a slave. And the prefetching controller also directs a second select circuit to transfer the prefetched data which is corresponding to the prefetching address signal from the slave to a master.

Abstract: A microprocessor includes an MSR and fuses. The microprocessor encounters an instruction requesting access to the MSR and specifying the MSR address, performs a function of the specified MSR address and a value read from the fuses to generate a first result, encrypts the first result with a secret key to generate a second result, compares the second result with an instruction-specified password, and allows the instruction to access the MSR if the second result matches the password and otherwise denies access MSR. Manufacturing subsequent instances of the microprocessor with a different fuse value effectively revokes the password. Alternatively, a control register of the microprocessor may be written by system software to override the fuse value and thereby revoke the password. The function may be XOR or concatenation, the encryption may be AES, and the secret key is externally invisible.

Abstract: A device for protecting a servo in reading signals on a defect disc from disturbance and instability is provided. The device includes a defect detection unit and a logic combination unit. The defect detection unit receives a plurality of defect detection signals to detect various defects for setting a plurality of defect flag signals, wherein the plurality of defect detection signals at least include an envelope signal of a RF signal and bit modulation signals. The logic combination unit performs logic operation on the defect flag signals in order to detect a specified defect. The logic combination unit indicates a servo control unit generating low-pass output signals according to said plurality of defect flag signals for controlling related electromechanical devices to prevent from disturbance and instability when the specified defect is detected. A method for protecting a servo in reading signals on a defect disc is also provided.

Abstract: A system and method for dual mode DP and HDMI transmission are provided. Briefly described, one embodiment of a dual mode DP and HDMI transmitter, among others, can be implemented as follows. The dual mode DP and HDMI transmitter comprises a driver circuit controlled by a data signal. The dual mode DP and HDMI transmitter also comprises a control circuit coupled to the driver circuit. The control circuit is configurable to transmit the data signal in a DP mode or a HDMI mode according to a mode signal. One embodiment of a method, among others, comprises: receiving a mode signal; determining whether to configure the dual mode DP and HDMI transmitter for transmitting in a DP mode or an HDMI mode based on the received mode signal; and configuring a dual mode DP and HDMI transmitter in accordance with the determination.

Abstract: Embodiments of systems and methods for managing a constant buffer with rendering context specific data in multithreaded parallel computational GPU core are disclosed. Briefly described, one method embodiment, among others, comprises responsive to a first shader operation, receiving at a constant buffer a first group of constants corresponding to a first rendering context, and responsive to a second shader operation, receiving at the constant buffer a second group of constants corresponding to a second context without flushing the first group.

Abstract: A cache memory system includes a first array of storage elements each configured to store a cache line, a second array of storage elements corresponding to the first array of storage elements each configured to store a first partial status of the cache line in the corresponding storage element of the first array, and a third array of storage elements corresponding to the first array of storage elements each configured to store a second partial status of the cache line in the corresponding storage element of the first array. The second partial status indicates whether or not the cache line has been modified. When the cache memory system modifies the cache line within a storage element of the first array, it writes only the second partial status in the corresponding storage element of the third array to indicate that the cache line has been modified but refrains from writing the first partial status in the corresponding storage element of the second array.

Abstract: A hard drive assessing method and a hard drive assessing system supporting a maximum transmission rate of a hard drive are provided, wherein the hard drive is accessed by a controller, and both the controller and the hard drive support a plurality of transmission rates. The maximum transmission rate of the hard drive is first obtained. When the controller reads data from the hard drive, the transmission rate of the controller is set to be not lower than the maximum transmission rate, and the transmission rate of the hard drive is maintained at the maximum transmission rate. When the controller writes data into the hard drive, the transmission rate of the controller is reduced to be lower than the maximum transmission rate, and the transmission rate of the hard drive is maintained at the maximum transmission rate. Thereby, the hard drive can be accessed at its maximum transmission rate.

Abstract: A microprocessor includes first and second functional units and a data cache having a data array having a write port, a modified bit array having a read port and a write port, and a tag array having a read port, each array having the corresponding predetermined organization. The first functional unit writes data to a cache line of the data array. The first functional unit sets a modified bit in the modified bit array to indicate that the corresponding cache line in the data array has been modified. The second functional unit reads the modified bit from the modified bit array to determine whether or not the cache line has been modified. The second functional unit reads a partial status of the corresponding cache line from the tag array. The partial status does not indicate whether the cache line has been modified. The tag array does not include a port by which the first functional unit may update the partial status of the corresponding cache line.

Abstract: A method for determining the boundary strengths of edges in a block-based digitally encoded image is disclosed. The method includes setting the boundary strength of two adjacent blocks in an Inter macroblock to a first strength value if any one of the two adjacent blocks contains non-zero prediction residual in the encoding data and setting the boundary strength thereof to a second strength value if the two adjacent blocks are located in the same motion compensation block. An edge with boundary strength equal to the second strength value will be skipped in a deblocking process.

Abstract: A pre-fetch controller for pre-fetching data from a memory and providing data to a logic operation unit is disclosed. The pre-fetch controller includes a register for storing a counter value and a controller connected to the register for changing the counter value when a pre-fetching is activated and for changing the counter value when a cache hit occurs.

Abstract: The present invention is directed to a method for rendering a computer graphics primitive intersected with one or more user-defined clipping planes. The method includes receiving a primitive, a clipping plane and a default scissor window; determining a second scissor window according to the spatial relationship among a first scissor window, the clipping plane and the vertices of the primitive; determining a group of pixels to be rendered by eliminating pixels not covered by an adjusted scissor window from the primitive; and determining a group of actually rendered pixels, in which the actually rendered pixels determining step includes removing the pixels meeting a clipping criterion from the group of pixels to be rendered. The present invention also includes an apparatus for performing the method.

Abstract: A format converting and recording method and system for optical storage media including the steps of converting several first optical storage medium information files into the second optical storage medium through generating corresponding navigation tables which gather at a management file, transmitting image of the first optical storage medium to the second optical storage medium, and then generating a destination disc according to the management file. Thus, the operation process is simplified and the problem of lacking in playback control is solved.

Abstract: A microprocessor includes an instruction translator that translates PUSHF, POP, and MOVSB x86 macroinstructions into multiple microinstructions that include a fused store microinstruction. For PUSHF, first and second microinstructions moves the x86 EFLAGS register into and mask off bits in a temporary register, and the fused store microinstruction stores it to a memory location. For POP, a first microinstruction loads a first memory location value into a temporary register and the fused store microinstruction stores it to the second memory location. For MOVSB, the first microinstruction loads a first memory location operand into a temporary register and the fused store microinstruction stores it to a second memory location. A reorder buffer receives the fused store microinstruction into exactly one entry.

Abstract: Systems and methods for compressing data within a block of data for storage in memory and for transmission along a data path are described herein. By utilizing previously unused bits in data words, the valid data can be stored more efficiently and transmitted in fewer transfer cycles, thereby increasing the availability of the data bus to other masters. One embodiment of a system for storing and transmitting compressed data includes masters and slaves interconnected by a data bus. One of the masters is a video input interface configured to receive video data from an external video source. The video input interface is further configured to compress the video data using a compression algorithm based on the difference in color between two adjacent pixels. Another one of the masters is a video display controller configured to receive the compressed video data.