Abstract: A semiconductor device includes a first group of trench-like structures and a second group of trench-like structures. Each trench-like structure in the first group includes a gate electrode contacted to gate metal and a source electrode contacted to source metal. Each of the trench-like structures in the second group is disabled. The second group of disabled trench-like structures is interleaved with the first group of trench-like structures.

Abstract: An ultra-short channel hybrid power field effect transistor (FET) device lets current flow from bulk silicon without npn parasitic. This device does not have body but still have body diode with low forward voltage at high current rating. The device includes a JFET component, a first accumulation MOSFET disposed adjacent to the JFET component, and a second accumulation MOSFET disposed adjacent to the JFET component at the bottom of the trench end, or a MOSFET with an isolated gate connecting the source.

Abstract: Method of forming a Hybrid Split Gate Semiconductor. In accordance with a method embodiment of the present invention, a plurality of first trenches is formed in a semiconductor substrate to a first depth. A plurality of second trenches is formed in the semiconductor substrate to a second depth. The first plurality of trenches are parallel with the second plurality of trenches. The trenches of the plurality of first trenches alternate with and are adjacent to trenches of the plurality of second trenches.

Abstract: In an embodiment in accordance with the present invention, a semiconductor device includes a vertical channel region, a gate at a first depth on a first side of the vertical channel region, a shield electrode at a second depth on the first side of the vertical channel region, and a hybrid gate at the first depth on a second side of the vertical channel region. The region below the hybrid gate on the second side of the vertical channel region is free of any electrodes.

Abstract: A boost converter circuit that includes a power supply, an inductor coupled to the power supply to receive current from the power supply, a diode coupled to receive current from the inductor and coupled to provide current to a load as an output, an inductor switch coupled to a node between the inductor and the diode for selectively switching current from the inductor anyway from the diode, and a ramp circuit. The ramp circuit is coupled to the node between the inductor and the diode, and is configured to selectively sample a voltage at the node between the inductor and the diode via a sampling switch and use the sampled signal to produce a stabilization ramp to stabilize the output.

Abstract: Embodiments of the present invention are directed toward a trench metal-oxide-semiconductor field effect transistor (TMOSFET) device. The TMOSFET device includes a source-side-gate TMOSFET coupled to a drain-side-gate TMOSFET 1203. A switching node metal layer couples the drain of the source-side-gate TMOSFET to the source of the drain-side-gate TMOSFET so that the TMOSFETs are packaged as a stacked or lateral device.

Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

Abstract: A method of fabricating a self-aligned contact in a semiconductor device, in accordance with one embodiment of the present invention, includes etching a trench in a core area and partially extending into a termination area of a substrate. A first oxide is grown on the substrate proximate the trench. A polysilicon layer is deposited in the core area and the termination area. The polysilicon layer is selectively etched to form a gate region in the core area portion of the trench. The etching of the polysilicon layer also forms a first portion of a gate interconnect region in the termination area portion of the trench and a second portion in the termination area outside of the trench.

Abstract: Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

Abstract: An LDMOS (laterally diffused metal oxide semiconductor) structure connects the source to a substrate and also the gate shield while utilizing a reduced area for such contacts. The structure includes an electrically conductive substrate layer, a source, and a drain contact; the drain contact is separated from the substrate layer by at least one intervening layer. An electrically conductive trench-like feed-through element passes through the intervening layer and contacts the substrate and the source to electrically connect the drain contact and the substrate layer.

Abstract: First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed.

Abstract: A split gate field effect transistor device. The device includes a split gate structure having a trench, a gate electrode and a source electrode. A first poly layer is disposed within the trench and is connected to the gate electrode. A second poly layer connected to the source electrode, wherein the first poly layer and the second poly layer are independent.

Abstract: A power switch with active snubber. In accordance with a first embodiment, an electronic circuit includes a first power semiconductor device and a second power semiconductor device coupled to the first power semiconductor device. The second power semiconductor device is configured to oppose ringing of the first power semiconductor device.

Abstract: The present technology is directed toward semiconductors packaged by electrically coupling a plurality of die to an upper and lower lead frame. The opposite edges of each corresponding set of leads in the upper lead frame are bent. The leads in the upper lead frame are electrically coupled between respective contacts on respective die and respective lower portion of the leads in the lower lead frame. The bent opposite edges of each corresponding set of leads of the upper lead frame support the upper lead frame before encapsulation, for achieving a desired position of the plurality of die between the leads of the upper and lower lead frames in the packaged semiconductor. After the encapsulated die are separated, the upper leads have an L-shape and electrically couple die contacts on upper side of the die to leads on the lower side of the die so that the package contacts are on the same side of the semiconductor package.

Abstract: A process for forming a Schottky barrier to silicon to a bather height selected at a value between 640 meV and 840 meV employs the deposition of a platinum or nickel film atop the silicon surface followed by the deposition of the other of a platinum or nickel film atop the first film. The two films are then exposed to anneal steps at suitable temperatures to cause their interdiffusion and a ultimate formation of Ni2Si and Pt2Si contacts to the silicon surface. The final silicide has a barrier height between that of the Pt and Ni, and will depend on the initial thicknesses of the Pt and Ni films and annealing temperature and time. Oxygen is injected into the system to form an SiO2 passivation layer to improve the self aligned process.

Abstract: One embodiment of the invention is a compensation circuit that includes a comparator that is coupled to receive a reference voltage. The compensation circuit can also include a capacitance coupled to receive a feedback voltage associated with an output voltage of a converter. Furthermore, the compensation circuit can include an adjustable resistance that is coupled to the capacitance and to the comparator.

Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Abstract: A trench metal-oxide-semiconductor field effect transistor (TMOSFET) includes a plurality of mesas disposed between a plurality of gate regions. Each mesa includes a drift region and a body region. The width of the mesa is in the order of quantum well dimension at the interface between the gate insulator regions and the body regions The TMOSFET also includes a plurality of gate insulator regions disposed between the gate regions and the body regions, drift regions, and drain region. The thickness of the gate insulator regions between the gate regions and the drain region results in a gate-to-drain electric field in an OFF-state that is substantially lateral aiding to deplete the charge in the drift regions.

Abstract: A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp corner where the gate oxide layer meets the sidewalls of the trench.

Abstract: A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown within the plurality of trenches. Gate polysilicon can be deposited within the plurality of trenches. Moreover, the method can include chemical mechanical polishing the gate polysilicon. The method can also include etching back the gate polysilicon within the plurality of trenches.