Abstract: The present invention provides for a circuit comprising: an input operable to receive a bit pattern; a shifter configured to selectively shift the bit pattern; a data output operable to output the bit pattern; and a sign extension operator coupled with the data output and operable to provide a sign extension signal thereto. The present invention additionally discloses a barrel shifter and a method for manipulating a bit pattern.

Abstract: The present invention is directed to a method and apparatus for detecting edges through one or more opaque, planarized layers of material. Exemplary embodiments can take full advantage of decreased size geometries associated, such as 0.25 micron technologies, without suffering inaccuracies due to wafer misalignment during processing (e.g., during a photolithographic process). The invention is applicable to any process where an edge is to be detected through a planarized layer which is opaque to visible light. In an exemplary embodiment, an edge of an alignment mark can be detected using an energy source having a wavelength and angle of incidence specifically selected with respect to the optical characteristics and thickness of particular material layers being processed.

Abstract: Non-power-of-two Gray-code counters, including modulos 10, 12, 14, and 22 are disclosed, along with a sequencing method they employ. Each counter includes a register for storing an N-bit, e.g., 4-bit, Gray-code count. The count is converted to binary code by a Gray-to-binary-code counter. The resulting binary count is incremented by an N-bit incrementer that skips certain binary values by toggling least-significant bits in unison when indicated by certain most-significant binary bits. The result is converted to Gray-code by a binary-to-Gray-code translator. The translated result is stored in the register as the next count. An algorithm is disclosed for designing such a Gray-code counter for any even modulo. The modulo is expressed as a sum of positive and negative terms, each term being a power of two. The exponents of the terms determine the counter design.

Abstract: A method for optimizing the performance of a 64-bit PCI initiator when transferring a 64-bit data via a 64-bit PCI bus. The 64-bit PCI initiator receives a single 64-bit data for transfer via the 64-bit PCI bus. The 64-bit PCI initiator breaks the 64-bit data into a first 32-bit data and a second 32-bit data. The 64-bit initiator then initiates a data transaction with the target device arbitrating for ownership of the 64-bit PCI bus. Upon receiving ownership of the 64-bit PCI bus, the 64-bit PCI initiator transfers the first 32-bit data and then transfers the second 32-bit data to the target device via the 64-bit PCI bus. The first 32-bit data and the second 32-bit data are transferred by the 64-bit PCI initiator to the target device without the assertion of a REQ64# signal, such that a REQ64# ACK64# protocol is avoided, enabling a more efficient completion of the data transaction.

Abstract: A method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. The trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further device processing steps. The barrier layer may also be deposited over the surface of the substrate to protect it from damage during device processing. The barrier layer may be removed by an etchant having a selectivity for the barrier layer over that of the surrounding device elements. Final processing of the device may be completed once the barrier layer is removed.

Abstract: A computer implemented circuit synthesis system includes a memory, an automatic test pattern generation (ATPG) algorithm, and processing circuitry. The memory is configured to provide a database, and is operative to store a netlist including nets of an integrated circuit under design. The automatic test pattern generation (ATPG) algorithm is operative to design and test an integrated circuit design.

Abstract: Disclosed is a technique to provide an integrated circuit substrate with a transistor gate member that has opposing sidewalls. A first spacer extends from one of the sidewalls and a second spacer extends from another of the sidewalls. A source region and a drain region of the substrate are doped, with the first and second spacers correspondingly masking first and second regions of the substrate. The first and second spacers are removed after doping and the first and second regions are exposed. The exposed first and second regions are then doped. The substrate is heated after this second doping stage to simultaneously activate dopant in the source region, the drain region, the first region, and the second region. A third spacer is then formed on the first region and a fourth spacer is then formed on the second region. A suicide contact is established with at least the transistor member, the source region, or the drain region after formation of the third and fourth spacers.

Abstract: After a metal deposition preclean, a very thin titanium layer is deposited followed by a thick nickel layer on a semiconductor silicon substrate. The titanium and nickel are deposited sequentially in a vacuum cluster tool to prevent oxidation of titanium in air. The silicon substrate and the metal layers are subject to a relatively low temperature anneal. The annealing causes the titanium to act as a reductant to break up the residual surface oxide on the surface of the silicon substrate and allows the nickel to react with the silicon substrate to form nickel silicide.

Abstract: The present invention provides methods of transmitting information within a personal handy-phone system wireless local loop and personal handy-phone system wireless local loops. One embodiment of a personal handy-phone system wireless local loop according to the present invention comprises: a base station; a repeater station configured to transmit a plurality of uplink radio signals to the base station and receive a plurality of downlink radio signals from the base station; and a portable station configured to transmit the downlink radio signals to the repeater station and receive the uplink radio signals from the repeater station.

Abstract: A system and method that prevents address aliasing and eliminates the unnecessary clock cycle consumed by the use of a dual address cycle when using a single address cycle to transmit a target address in a computer system including target devices having addresses of different sizes, such as 32-bit and 64-bit target devices, with 32-bit and 64-bit addresses, respectively. In addition, a combination of single address cycles and dual address cycles may be used to prevent address aliasing while permitting access to the entire address spaces of the target devices. The computer system includes a bus, an initiator device coupled to the bus, a first target device coupled to the bus, and a second target device coupled to the bus. The first target device has a first address range containing a plurality of bits, and the second target device has a second address range containing a fewer number of bits than the first address range.

Abstract: The present invention is a direct access bridge for translating messages between a first protocol and a second protocol via a first component interface and a second component interface. The first and second component interfaces are adapted to respectively couple to a first and second protocol bus. The first component interface is also coupled to the second component interface. The first component interface is further adapted to transmit and receive data and fundamental message information to and from a first component via the first protocol bus using the first protocol. The second component interface transmits and receives the data and the fundamental message information to and from the second protocol bus in accordance with the second protocol. Similarly, the second component interface and the first component interface transform the data and fundamental message information from the first protocol to the second protocol and vice versa between the first and second bus.

Abstract: The present invention relates to semiconductor devices in general, and more particularly to semiconductor devices having anti-reflective coatings to aid in the patterning of a reflective layer thereon to form, for example, a gate electrode. The invention also relates to methods for making a semiconductor having a patterned reflective layer.

Abstract: A built-in-self-test circuit aids in testing a phase locked loop circuit. The phased locked loop has a plurality of frequency multipliers. The built-in-self-test circuit includes a frequency divider and a multiplexer. The frequency divider has a plurality of divide-by-counters. For each frequency multiplier within the plurality of frequency multipliers there is a corresponding divide-by-counter. A ratio of a multiplier for each frequency multiplier to a divider of its corresponding divide-by-counter is a constant for all frequency multipliers and corresponding divide-by-counters. When a frequency multiplier within the plurality of frequency multipliers is selected, the multiplexer selects its corresponding divide-by-counter to produce a test output clock.

Abstract: The present invention is a simulation tool input file generator implemented in a computer system that permits a designer to efficiently and effectively create and modify electrical circuit simulation tool input files. The simulation tool input file generator permits a user to conveniently enter high level circuit description information in user friendly formats such as an easy to use GUI. Based upon the information provided by a user, the present invention assembles data including circuit description files stored in a memory and produces a detailed simulation tool input files.

Abstract: An integrated circuit device including a FIFO and a clock generator having a pulse swallower. The pulse swallower eliminates pulses from a reference frequency signal, producing a primary digital transceiver clock signal having a frequency of chiprate(S)(n), which is used to clock a digital transceiver when the device is in a primary mode. A first clock divider divides the frequency of the primary digital transceiver clock signal to produce a FIFO output clock signal having a frequency of chiprate(S). The FIFO has a data bus input for coupling to a data output, for example from an analog transceiver. The FIFO also has an external clock input for coupling to a clock output, for example from the analog transceiver. The external clock signal clocks the data into the FIFO asynchronous with the primary digital transceiver clock signal at a frequency of chiprate(S). The internal clock signal clocks the data out of the FIFO, synchronous with the primary digital transceiver clock signal at a frequency of chiprate (S).

Abstract: Multiple cryptographic algorithms are utilized on a single integrated circuit. In a single special memory, a plurality of values are stored. The values are used for a first cryptographic algorithm and are used for a second cryptographic algorithm. At least one value from the plurality of values is used both for the first cryptographic algorithm and for the second cryptographic algorithm. When performing a first operation for the first cryptographic algorithm, first values from the plurality of values are used. The first values include the value used both for the first cryptographic algorithm and for the second cryptographic algorithm. When performing a second operation for the second cryptographic algorithm, second values from the plurality values are used. The second values also include the value used both for the first cryptographic algorithm and for the second cryptographic algorithm.

Abstract: A system and method for completing a read transaction between an initiator device and a host memory device in a computer system, in which the present invention optimizes the retry behavior of the initiator device and a target device. The system of the present invention includes a bus bridge device, wherein the bus bridge device includes a target device coupled to the initiator device via a bus; the host memory device coupled to the bus bridge device; and a timer mechanism coupled to the target device. The initiator device is adapted to initiate a present read transaction via the target device, such that an access is asserted between the initiator device and the target device. The timer mechanism is adapted to measure target latency for one or more read transactions preceding the present read transaction, and the timer mechanism is further adapted to use the target latency to calculate a dynamic target latency period.

Abstract: Comparators, memory devices, comparison methods and memory reading methods are provided. One aspect provides a comparator including an input stage having a data input adapted to receive a data voltage signal, a reference input adapted to receive a reference voltage signal, and a plurality of current sources individually coupled with one of the data input and the reference input and individually configured to convert one of the data voltage signal and the reference voltage signal to a differential current signal and to output the differential current signal; and a comparator stage including a plurality of inputs configured to receive the differential current signals from the input stage and the comparator stage being configured to compare the differential current signals and to output an output signal indicative of a comparison of the differential current signals.

Abstract: An electronic device for receiving infra-red inputs from remote units and propagating the inputs to an intelligent controller circuit. In one embodiment, the present invention receives the infra-red energy emitted from different remote units in a single infra-red receiver circuit. This embodiment then generates digital data signals responsive to the infra-red energy, and propagates the digital data signals through a single external single-pin bus to an integrated circuit. The integrated circuit contains circuitry therein to decode control signals from a variety of different remote units. In this embodiment, the integrated circuit's internal bus is coupled to the single external single-pin bus. The internal bus is commonly coupled to all remote control decoder circuits within the integrated circuit.

Abstract: A pulse density modulator generates output pulses that are optimized as to their even distribution over time. More particularly, the invention represents parallel or serial digital input signals as serial binary output signals, where the binary output pulses are evenly spaced over time to the greatest extent possible. The output signal includes a pattern that repeats during successive “cycles.” The number of pulses in each cycle varies in proportion to the magnitude of the digital input signal. When a digital input signal is provided to an accumulator, the accumulator repeatedly updates a current N-bit sum value by adding the digital input signal thereto. According to this computation, the accumulator either (1) provides a first prescribed signal on a carry output if the current sum cannot be expressed in N bits, or (2) provides a different prescribed signal on the carry output if the current sum can be expressed in N bits.