Patents Assigned to VLSI Technology, Inc.
  • Publication number: 20020029744
    Abstract: In the manufacture of a semiconductor device, an arrangement for forming a layer on a semiconductor substrate compensates for variations in wafer substrate reflectivity. The arrangement includes providing substrate illumination and then adjusting the illumination on the substrate. The arrangement also includes controlling the dispensation of material over the substrate as a function of the adjusted illumination. By compensating for variations in wafer substrate reflectivity, manufacturing processes can realize more consistent photoresist coatings on wafer substrates from one wafer lot to another.
    Type: Application
    Filed: November 16, 2001
    Publication date: March 14, 2002
    Applicant: VLSI Technology, Inc. (Koninklijke Philips Electronics N.V.).
    Inventor: Daniel C. Baker
  • Patent number: 6354921
    Abstract: An apparatus to induce very small bubbles of gas into a stream of deionized water without allowing large bubbles to be entrained is disclosed for use in Chemical Mechanical Polishing for semiconductor manufacture. The apparatus includes a cylinder possessing a central axis positioned vertically, a gas inlet, a deionized water inlet positioned essentially above the gas inlet, a deionized water with gas outlet positioned essentially above the deionized water inlet and a vent outlet positioned essentially above the deionized water with gas outlet. The apparatus introduces an essentially gaseous composition into the cylinder through the gas inlet into deionized water in the cylinder. The gas travels through the deionized water inlet to a level in the cylinder above the position of the deionized water with gas outlet, wherein the gaseous composition is further constrained to enter as bubbles with a predetermined size range in the deionized water through the deionized water inlet.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: March 12, 2002
    Assignee: VLSI Technology Inc.
    Inventors: Alexander P. Wood, Oscar L. Caton
  • Patent number: 6356610
    Abstract: A system to avoid unstable data transfer between digital systems. The present invention includes a system that enables digital systems to communicate while avoiding unstable data transfer, which can result in a loss of data or signal distortion. For instance, the present invention includes a system that enables detection of potentially unstable operating conditions for a digital receiver device during its reception of clock and digital data signals from a digital transmitter device. One embodiment of the present invention monitors the received clock and digital data signals in order to detect any potential violations of the internal input timing requirement of the digital receiver device. If any potential violations of the input timing requirement are detected, the present invention invokes measures to eliminate them by manipulating the phase of the clock signal utilized internally by the digital receiver device to sample the received digital data signals.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: March 12, 2002
    Assignee: VLSI Technology, Inc.
    Inventor: Stefan Ott
  • Patent number: 6355576
    Abstract: A method for cleaning bonding pads on a semiconductor device, as disclosed herein, includes treating the bonding pads with a CF4 and water vapor combination. In the process, the water vapor breaks up and the hydrogen from the water vapor couples to fluorine residue on the bonding pad surface creating a volatile HF vapor. In addition, fluorine from the CF4 exchanges with the titanium in the metallic polymer residue making the polymer more soluble for the organic strip operation which follows. Next, the resist is ashed and then an organic resist stripper is applied to the bonding pad area, thereby creating a clean bonding pad surface. Thereafter, a reliable bond wire connection can be made to the bonding pad.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: March 12, 2002
    Assignee: VLSI Technology Inc.
    Inventors: Mark Haley, Delbert Parks, Judy Galloway
  • Patent number: 6353904
    Abstract: A method of automatically generating a mixed-signal test program. The method according to one embodiment of the present invention is implemented in software in the form of two software processes. The first software process of the present embodiment includes a test-block extraction process which allows a user to extract re-usable test data from pre-existing test programs. The extracted re-usable test data is then stored in a template library in the form of a template. In one embodiment, the user only needs to provide the names of the interested cells and the corresponding pin designations to extract relevant test data from pre-exisiting test programs. The second software process of the present embodiment includes a test-block retargeting process which allows a user to use test data stored in the template library in a new mixed-signal test program. The names of the analog cells used in a new mixed-signal integrated design are provided to the test-block retargeting process.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: March 5, 2002
    Assignee: VLSI Technology, Inc.
    Inventor: Dai Minh Le
  • Patent number: 6353368
    Abstract: A low phase noise CMOS voltage controlled oscillator (VCO) circuit. The VCO circuit includes a bias circuit and a VCO cell coupled to the bias circuit. The VCO cell includes a VCO output for transmitting a VCO output signal. A frequency to voltage converter is coupled to receive the VCO output signal. The frequency to voltage converter converts a frequency of the VCO output signal into a corresponding voltage output. The voltage output is coupled to control the bias circuit. The VCO cell includes a current source coupled to the bias circuit such that the voltage output from the voltage a current converter provides negative feedback to the VCO cell via the current source. The negative feedback, in turn, reduces the phase noise on the VCO output signal.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: March 5, 2002
    Assignee: VLSI Technology, Inc.
    Inventor: Kamran Iravani
  • Patent number: 6353261
    Abstract: An apparatus for reducing interconnect resistance using optimized trench geometry. One embodiment comprises an interconnect line and an interconnect well. The interconnect line, comprised of a conductive material, has a depth and exists in a first circuit layer of a multilayered Integrated Circuit (IC). The interconnect well is coupled to the interconnect line and is insulated from other conductive materials in the first circuit layer, and in the plurality of subsequent adjacent layers. The interconnect well has a depth in said multilayered IC that exceeds said depth of said interconnect line.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: March 5, 2002
    Assignee: VLSI Technology, Inc.
    Inventor: Milind Weling
  • Patent number: 6346032
    Abstract: The present invention is a fluid dispensing fixed abrasive polishing pad CMP system and method that utilizes fixed abrasive components to remove a portion or entire layer of a wafer while dispensing a fluid without suspended abrasive particles onto the wafer surface. A fluid dispensing fixed abrasive polishing pad is pressed against a wafer surface while rotating and fixed abrasive component apply a frictional force that planarizes a wafer surface. The fluid dispensed by the fluid dispensing fixed abrasive polishing pad assist the fixed components achieve wafer planarization in numerous ways, including minimizing scratching of the wafer surface, chemically reacting with the wafer surface to soften it, and aiding in the removal of particulate contaminants. The fluid flow in the present invention is strong enough to remove the waste (e.g., reaction products, wafer shavings, particulate contaminants, etc.) from the surface of the wafer and the fixed abrasive polishing pad during the polishing process.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: February 12, 2002
    Assignee: VLSI Technology, Inc.
    Inventors: Liming Zhang, Andrew Black, Landon Vines
  • Patent number: 6341998
    Abstract: The present invention system and method facilitates efficient material deposition and wafer planarization during IC wafer fabrication. The present invention is particularly useful in facilitating efficient copper deposition and manufacturing of interconnections between components of an IC. A deposition polishing system and method of the present invention performs copper deposition and polishing concurrently. One embodiment of a deposition polishing system comprises a wafer holder, polishing pad component, and CMP plating bath. The CMP plating bath is a container for holding solutions utilized in plating processes (e.g., electroplating, electroless plating, etc.) to deposit metallic material (e.g., copper) on a wafer.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: January 29, 2002
    Assignee: VLSI Technology, Inc.
    Inventor: Liming Zhang
  • Patent number: 6341362
    Abstract: An extended symbol Galois field error correcting device is provided. The device includes a singly-extended Reed-Solomon encoder configured to generate an encoded codeword, {tilde over (c)}(x). The device also includes a channel medium that is signal coupled with the singly-extended Reed-Solomon encoder. The channel medium is configured to receive the encoded codeword, {tilde over (c)}(x), and output a received input codeword, {tilde over (r)}(x). The channel medium is capable of introducing error, {tilde over (e)}(x), to the encoded codeword, {tilde over (c)}(x). The device further includes a singly-extended Reed-Solomon decoder that is coupled with the channel medium. The singly-extended Reed-Solomon decoder is configured to receive the received input codeword, {tilde over (r)}(x). The singly-extended Reed-Solomon decoder has error detection circuitry and extended symbol correction circuitry.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: January 22, 2002
    Assignee: VLSI Technology, Inc.
    Inventor: Habibollah Golnabi
  • Patent number: 6338158
    Abstract: Testing and validation of custom IC designs is performed using standard ICs. Highly complex integrated circuits, instead of being designed at the gates and flops level, are typically designed using standardized cell libraries that allow for widespread, systematic design reuse. Such libraries may include Functional System Blocks, or FSBs (sometimes referred to as ASIC cores), and Application Specific Standard Parts (ASSPs). ASSPs are designs that are or were once realized as stand-alone parts, but that may also be embedded into larger designs (“embedded ASSPs”). Instead of a conventional software model, testing and validation is performed using a hardware model of a custom integrated circuit. The hardware model may be a breadboard system that is decomposed into three levels of functionality: ASSPs, FSBs and “glue logic”ASSPs are typically 500K gates or more and may be realized as separate ICs. FSBs are typically 50K gates or less.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: January 8, 2002
    Assignee: VLSI Technology, Inc.
    Inventor: Robert L. Payne
  • Patent number: 6330623
    Abstract: A direct memory access engine (DMA) system and method for maximizing DMA transfers of arbitrarily aligned data. The present invention utilizes physical region descriptors (PRD) stored in memory to track locations and descriptions of scattered data in a main memory. The direct memory access circuit retrieves the data in accordance with the PRD and configures the data into pieces such that intermediate pieces of data between a first piece and a last piece are the maximum amount of information a communication burst is capable of transferring and the intermediate pieces of data are aligned to a natural boundary address. The DMA engine also communicates the first piece of data and the last piece of data in a manner that minimizes memory accesses and in transfer sizes that are compatible with requirements and limitations of a system in which DMA engine is implemented.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: December 11, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Shih-ho Wu, David Ross Evoy
  • Patent number: 6327513
    Abstract: Methods and apparatus for calculating alignment of layers during semiconductor processing are described. In one embodiment, first and second alignment targets are formed over a substrate and include respective pairs of first and second alignment target edges. The second alignment target defines a point of reference. First and second distances are measured between the first alignment target edges and the second alignment target edges as respective first and second functions of the distance from the point of reference. The first and second functions are differenced to define a linear equation having a slope and an intercept which contains offset components in two different directions. In a preferred embodiment, third and fourth alignment targets are formed over the substrate, with the fourth alignment target defining a different point of reference.
    Type: Grant
    Filed: April 16, 1998
    Date of Patent: December 4, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: David Ziger
  • Patent number: 6326283
    Abstract: An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. An oxidation of the substrate is performed to provide for round corners at a perimeter of the trench area. The substrate is then etched to form a trench within the trench area.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: December 4, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Victor Liang, Olivier Laparra, Mark Rubin
  • Patent number: 6323520
    Abstract: A method for forming a semiconductor device with a doped channel-region, and the device formed therefrom. In one embodiment, the method invention is comprised of two principal steps. The first step is to provide a semiconductor substrate to which the following process steps can be performed. The second step is to create a doping profile into the channel-region of the semiconductor substrate. The doping profile is created by a) performing a first doping implantation with a first dopant in a first concentration to a first depth within the semiconductor substrate, and b) performing a second doping implantation with a second dopant in a second concentration to a second depth within the semiconductor substrate.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: November 27, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Samar Kanti Saha
  • Patent number: 6324663
    Abstract: The present invention is an on board internal peripheral component interconnect (PCI) bus tester for testing internal components of a microelectronic chip. The present invention includes internal PCI testing agents that facilitate the application of test vectors to internal PCI agents from a minimal number of external periphery pins on the chip. The on board internal peripheral component interconnect (PCI) bus tester then captures the state of an internal PCI bus and transmits it though the external periphery pins of the chip for analysis to determine if the internal agent components are functioning correctly.
    Type: Grant
    Filed: October 22, 1998
    Date of Patent: November 27, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Peter Chambers
  • Patent number: 6321321
    Abstract: A set-associative cache-management method utilizes both parallel reads and single-cycle single-set reads. The parallel reads involve accessing data from all cache sets in parallel before a tag match is determined. Once a tag match is determined, it is used to select the one of the accessed cache memory locations to be coupled to the processor for the read operation. Single-cycle single-set reads occur when the line address of one read operation matches the line address of a immediately preceding read operation satisfied from the cache. In such a case, only the set from which the previous read request was satisfied is accessed in the present read operation. If a sequential read operation is indicated, the same-set can also be accessed to the exclusion of the other sets provided the requested address does not correspond to the beginning of a line address. (In that case, the sequential read crosses a cache-line boundary.
    Type: Grant
    Filed: June 21, 1999
    Date of Patent: November 20, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Mark W. Johnson
  • Patent number: 6319796
    Abstract: Disclosed are techniques to provide an integrated circuit, including the provision of improved integrated circuit isolation structures. The techniques include forming a number of trenches in an integrated circuit substrate to define a number of substrate regions that are to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece. A number of components, such as insulated gate field effect transistors, may be subsequently formed in the substrate regions between the trenches.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: November 20, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Olivier Laparra, Ramiro Solis, Hunter Brugge, Michela S. Love, Bijan Moslehi, Milind Weling
  • Publication number: 20010041431
    Abstract: Useful to inhibit reverse engineering, semiconductor devices and methods therefor include formation of two active regions over a substrate region in the semiconductor device. According to an example embodiment, a dopable link, or region, between two heavily doped regions can be doped to achieve a first polarity type, with the two heavily doped regions of the opposite polarity. If dictated by design requirements, the dopable region is adapted to conductively link the two heavily doped regions. A dielectric is formed over the dopable region and extends over a portion of each of the two heavily doped regions to inhibit silicide formation over edges of the dopable region. In connection with a salicide process, a silicide is then formed adjacent the dielectric and formed over another portion of the two heavily doped regions.
    Type: Application
    Filed: July 24, 2001
    Publication date: November 15, 2001
    Applicant: VLSI TECHNOLOGY, INC.
    Inventors: Gregory Stuart Scott, Emmanuel de Muizon, Martin Harold Manley
  • Patent number: 6316834
    Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: November 13, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Calvin T. Gabriel, Dipankar Pramanik, Xi-Wei Lin