Patents Assigned to VLSI Technology, Inc.
  • Patent number: 6281822
    Abstract: A pulse density modulator generates output pulses that are optimized as to their even distribution over time. More particularly, the invention represents parallel or serial digital input signals as serial binary output signals, where the binary output pulses are evenly spaced over time to the greatest extent possible. The output signal includes a pattern that repeats during successive “cycles.” The number of pulses in each cycle varies in proportion to the magnitude of the digital input signal. When a digital input signal is provided to an accumulator, the accumulator repeatedly updates a current N-bit sum value by adding the digital input signal thereto. According to this computation, the accumulator either (1) provides a first prescribed signal on a carry output if the current sum cannot be expressed in N bits, or (2) provides a different prescribed signal on the carry output if the current sum can be expressed in N bits.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: August 28, 2001
    Assignees: Dot Wireless, Inc., VLSI Technology, Inc.
    Inventor: Edwin C. Park
  • Patent number: 6281880
    Abstract: An electronic device for receiving infra-red inputs from remote units and propagating the inputs to an intelligent controller circuit. In one embodiment, the present invention receives the infra-red energy emitted from different remote units in a single infra-red receiver circuit. This embodiment then generates digital data signals responsive to the infra-red energy, and propagates the digital data signals through a single external single-pin bus to an integrated circuit. The integrated circuit contains circuitry therein to decode control signals from a variety of different remote units. In this embodiment, the integrated circuit's internal bus is coupled to the single external single-pin bus. The internal bus is commonly coupled to all remote control decoder circuits within the integrated circuit.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: August 28, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Jerry Michael Rose, Kenneth A. Jaramillo
  • Patent number: 6282129
    Abstract: Comparators, memory devices, comparison methods and memory reading methods are provided. One aspect provides a comparator including an input stage having a data input adapted to receive a data voltage signal, a reference input adapted to receive a reference voltage signal, and a plurality of current sources individually coupled with one of the data input and the reference input and individually configured to convert one of the data voltage signal and the reference voltage signal to a differential current signal and to output the differential current signal; and a comparator stage including a plurality of inputs configured to receive the differential current signals from the input stage and the comparator stage being configured to compare the differential current signals and to output an output signal indicative of a comparison of the differential current signals.
    Type: Grant
    Filed: March 7, 2000
    Date of Patent: August 28, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Elie Georges Khoury, Richard W. Ulmer
  • Patent number: 6274940
    Abstract: A semiconductor wafer polishing method comprises forming at least one alignment mark within an alignment area on a semiconductor wafer, forming a layer to be polished over the wafer, the layer being formed to be generally elevationally higher proximately about and surrounding the alignment area than within the alignment area, and polishing the layer. According to another aspect, a semiconductor wafer includes an alignment marking area formed relative to a surface of the wafer. At least one alignment mark is provided within the alignment area. A structure is formed about the alignment marking area and extends from the wafer surface a greater elevation than any elevation from such surface from which the alignment mark extends. Furthermore, a layer of material to be polished is provided over the structure to cause the material to be polished to be elevationally higher over the structure than over the alignment mark.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: August 14, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Daniel Claire Baker, Charles Franklin Drill, Milind Ganesh Weling
  • Patent number: 6275694
    Abstract: A method for remotely updating software code of personal handy phone system equipment. The present invention enables a remotely located control terminal to update stored software code within a distant portable station or cell station of the personal handy phone system. Specifically, by coupling a control terminal to the existing communication network of a personal handy phone system, the control terminal is able to communicate with portable stations and cell stations. To update the software code of a specific portable station or cell station, the control terminal first establishes communication with that particular device by sending an unique preparatory signal addressed to it. The addressed device receives the unique preparatory signal and checks the validity of it. If the addressed device determines the unique preparatory signal is valid, it transmits a unique verification signal addressed to the control terminal indicating that it is ready to receive the updated version of the software code.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: August 14, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Satoshi Yoshida, Patrick Feyfant, Varenka Martin, Laurent Winckel, Philippe Gaglione, Oliver Weigelt, Denis Archambaud
  • Patent number: 6272439
    Abstract: A circuit for programmably generating a delay in a frequency monitor. In one embodiment, the circuit includes a delay cell. A delay cell controller is coupled to the delay cell. The delay cell controller is adapted to selectively control whether the delay cell is activated such that the frequency monitor can be programmably configured to have a selected delay associated therewith.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: August 7, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Mark L. Buer, David A. Auer
  • Patent number: 6272050
    Abstract: Exemplary embodiments are directed to providing a flash EEPROM technology which is compatible with deep submicron dimensions, and which is suitable for straightforward integration with high performance logic technologies. Unlike known technologies, exemplary embodiments provide a reduced cell area size in a split gate cell structure. An exemplary process for implementing a flash EEPROM in accordance with the present invention involves growing a tunneling oxide in a manner which reduces tunneling barrier height, and requires minimum perturabition to conventional high performance logic technologies, without compromising logic function performance.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: August 7, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: James A. Cunningham, Richard A. Blanchard
  • Publication number: 20010010228
    Abstract: The present invention is a method of suppressing etchrate of quartz hardware in semiconductor processing chamber during plasma-enhanced cleaning. In one embodiment, the method of the present invention comprises the steps of: (a) introducing a mixture of fluorocarbon gas, oxygen, and water vapor into the chamber; and (b) activating the mixture to form a quartz-safe plasma cleaning gas. According to the present invention, the presence of water vapor substantially suppresses etching of quartz hardware. Etchrate of the polymer contaminants, however, is substantially unaffected. In one embodiment of the invention, the fluorocarbon gas comprises CF4, and, water vapor is introduced at a rate of at least 60 standard cubic centimeters per minute (SCCM).
    Type: Application
    Filed: March 16, 1998
    Publication date: August 2, 2001
    Applicant: VLSI TECHNOLOGY, INC.
    Inventors: WING-KEI AU, RAMIRO SOLIS
  • Patent number: 6267076
    Abstract: A gas phase planarization process for semiconductor wafers. The present invention comprises a system and method of dry planarization for a semiconductor wafer. For instance, the present invention includes a system adapted to effectively remove all, or a portion of, a layer of dielectric material of a semiconductor wafer through the application of dry abrasion and dry chemistry. As such, a present invention system flattens out height differences of the dielectric material, since high areas of topography are removed faster than low areas.
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: July 31, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Rao V. Annapragada, Calvin T. Gabriel, Milind G. Weling
  • Publication number: 20010009838
    Abstract: A multi-platen chemical-mechanical polishing system is used to polish a wafer. The wafer is polished at a first station. During polishing, an endpoint is detected. The endpoint is detected by generating optical radiation by a first light source. The first optical radiation travels through a translucent area in a surface of a first platen and travels through a first polishing pad. After being reflected by the wafer, the optical radiation returns through the first polishing pad through the translucent window to a first optical radiation detector. The first polishing pad has a uniform surface in that no part of the surface of the first polishing pad includes transparent material through which non-scattered optical radiation originating from the first light source can pass and be detected by the first optical radiation detector. Optical radiation that travels through the first polishing pad and is detected by the first optical radiation detector is haze scattered by inclusions within the first polishing pad.
    Type: Application
    Filed: March 13, 2001
    Publication date: July 26, 2001
    Applicant: VLSI Technology, Inc.
    Inventors: Samuel Vance Dunton, Yizhi Xiong
  • Patent number: 6265252
    Abstract: An integrated circuit workpiece is provided having a polysilicon transistor gate member extending from a substrate. A pair of oxide spacers are formed on opposing sides of the gate member and a metal layer is deposited on the workpiece. The workpiece is heated to form a silicide region on the gate member and on selected regions of the substrate. A surface profile for each of the spacers is provided which has a progressively steeper slope from a rounded upper shoulder portion to a lower wall portion to control thickness of the metal layer on the gate member relative to thickness on the spacers. Formation of the spacers may include plasma etching with a gas mixture having from about 1 to about 20% molecular oxygen to steepen a slope of the surface profile of each of the spacers. Further, shaping of the spacers may be utilized to establish a ratio of the minimum thickness on the gate member to the minimum thickness on each spacer of at least about 2.5 to reduce silicide bridging of the spacers.
    Type: Grant
    Filed: May 3, 1999
    Date of Patent: July 24, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Xi-Wei Lin
  • Patent number: 6265904
    Abstract: A digital phase shift amplification and detection system and method for amplifying and detecting a phase shift. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region in which the applied signal transitions at a relatively close time to a trigger in the clock signal of the flip flop. The digital phase shift amplification and detection system and method amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect timing delays in the amplified signal. A signal is applied to a digital phase shift amplifier including a flip flop operated in the metastable region which amplifies any timing changes in the signal. The amplified signal is fed into a detection circuit configured to detect the amplified timing differences in the amplified signal as a result of a relatively smaller timing change in an input signal.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: July 24, 2001
    Assignee: VLSI Technology Inc.
    Inventor: Ray Killorn
  • Patent number: 6259710
    Abstract: A system for intelligent C-plane switching in the digital enhanced cordless telecommunications (DECT) system. The present invention includes a system that enables fast C-plane transmission mode during cordless telephone voice connections within the digital enhanced cordless telecommunications (DECT) system without degrading the voice quality. In order to perform this fast C-plane transmission mode during voice connections, one embodiment of the present invention, located within a cordless telephone handset, utilizes a silence detector circuit to determine the periods of silence within the voice data transmitted through the U-plane. By determining the periods of silence within the U-plane voice data, the present invention is able to direct the control data to be transmitted through the fast C-plane during the periods of silence.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: July 10, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Andreas Junghans
  • Patent number: 6258611
    Abstract: A method for determining translation portion of misalignment error in a stepper. In one embodiment, the method comprises a series of steps in a stepper, starting with the step of receiving a wafer in the stepper. In another step a first pattern, including an error-free fine alignment target, is created on the wafer. Next, the wafer is realigned in the stepper using the error-free fine alignment target. Then a second pattern is created on the wafer overlaying said first pattern. In another step, the translational error between the first pattern and the second pattern is measured.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: July 10, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Pierre Leroux
  • Patent number: 6260132
    Abstract: An address decoder includes a plurality of address decoder modules. Each address decoder module has a select line for each of a plurality of devices. Each of a plurality of XOR combination circuits performs a logic XOR function of all select lines for a single device from the plurality of devices. State control within the address decoder activates one address decoder module at a time.
    Type: Grant
    Filed: February 1, 1999
    Date of Patent: July 10, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Mark Leonard Buer
  • Patent number: 6256354
    Abstract: Voice recording and playback mode using the G.726 half-rate within the personal handy phone system (PHS). When a portable station within the PHS operates as a voice recorder (e.g., functioning as an answering machine), a cost effective system in accordance with the present invention is adapted to compress and store received voice/sound signals in order to increase the usage of limited memory resources provided within the portable station. The present invention also enables previously compressed and stored voice/sound signals to be decompressed and played back in various portable station playback modes. Specifically, the portable station receives a voice/sound signal in a full rate (e.g., 32 kilobits-per-second) 4-bit adaptive differential pulse code modulation (ADPCM) data format in compliance with the International Telecommunication Union (ITU) recommendation G.726.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: July 3, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Satoshi Yoshida, Patrick Feyfant, Philippe Gaglione, Denis Archambaud, Varenka Martin, Laurent Winckel, Rita Lagomarsino, Oliver Weigelt
  • Patent number: 6252813
    Abstract: A method and apparatus for programmable read only memory with high speed differential sensing at low operating voltage. In one embodiment, a programmable memory cell is comprised of word line, a bitline, and a transistor. The transistor, representing a single binary digit (bit), has a gate coupled to a word line, a drain coupled to a bitline, and a source capable of being programmed to provide a logic level of 0 and a logic level of 1. By programming the source of the transistor, the bitline approximately equal capacitance for both logic level 0 and logic level 1 states.
    Type: Grant
    Filed: January 4, 2000
    Date of Patent: June 26, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Kwo-Jen Liu
  • Patent number: 6244929
    Abstract: A chemical-mechanical-polishing system having a slurry distribution system, a polisher, a deionized water supply, and a drain, includes a slurry filtration system. The filtration system has two filters for alternately filtering particles in slurry and being backflushed with deionized water. Two input valves have input ports connected to the slurry distribution system and output ports respectively connected to the filters for filtering. Two output valves have input ports respectively connected to the filters for receiving filtered slurry and output ports connected to the polisher. Two backflush valves have input ports connected to the deionized water supply and output ports respectively connected to backflush with deionized water; the output ports are also respectively connected to the input ports of the two output valves. Two drain valves have input ports respectively connected to the filters for receiving backflushed fluid and output ports connected to the drain.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: June 12, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Richard D. Russ, Daniel Thomas
  • Patent number: 6246121
    Abstract: A flip-chip semiconductor device with generic bump patterns formed on a semiconductor substrate and having optimized electrical performance is provided. In a preferred embodiment, the flip-chip semiconductor device includes a semiconductor substrate on which active elements are formed and which has a surface having a plurality of peripheral portions, the active elements including Input/Output (I/O) circuitry and logic circuitry, a first power supply wiring and a first ground wiring disposed in the semiconductor substrate, a signal wiring disposed in the semiconductor substrate, and a first plurality of bumps arranged on the plurality of peripheral portions and selectively used for coupling the semiconductor substrate to a second substrate. The first plurality of bumps are arranged in a matrix pattern of 6 rows by n columns. Bumps in predetermined locations in the matrix are selectively coupled to the first power supply wiring and the first ground wiring.
    Type: Grant
    Filed: April 12, 1999
    Date of Patent: June 12, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Sanjay Dandia, Jayarama N. Shenoy
  • Patent number: 6242805
    Abstract: A method of using polish stop film to control dishing during copper chemical mechanical polishing. In one embodiment, the method comprises several steps. One step involves depositing a polish stop layer above a metal layer disposed on a semiconductor wafer. Another step involves placing the semiconductor wafer onto a polishing pad of a chemical mechanical polishing machine. A further step involves removing the metal layer of the semiconductor wafer and also preferentially removing the polish stop layer using a chemical mechanical polishing process. The benefit of the polish stop layer is to prevent dishing of the metal layer within the trench. Another step involves ceasing the chemical mechanical polishing process when the metal layer is removed from desired areas of the semiconductor wafer and the semiconductor wafer is substantially planar.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: June 5, 2001
    Assignee: VLSI Technology, Inc.
    Inventor: Milind Weling