Abstract: A computing system encodes and emulates requests signals, such as DMA requests or interrupt requests. A first peripheral device is connected to a first request pin of a first input/output (I/O) device. When the first peripheral device asserts a first request signal on the first request pin, a serializer within the first I/O device generates a first packet. The serializer forwards the first packet to a serial out port of the first I/O device. The first packet identifies the type of request and the direction of the edge transition. The serial out port forwards the first packet to a serial in port of a controller device. Upon the serial in port receiving the first packet, an unserializer within the controller device asserts an emulated first request signal, the emulated first request signal being coupled to a first request controller within the controller device.

Abstract: An integrated circuit system includes an integrated circuit with a heat sink assembly including a fusible core. In the event that power dissipation by the integrated circuit threatens to exceed its safe operating range, the fusible core melts, absorbing the heat of fusion and delaying further temperature increases. A motor is repeatedly activated to attempt to rotate a shaft within the fusible core. When the core is solid, the shaft cannot be turned, but once it melts the shaft turns. The shafts motion is detected and used to trigger a reduction in the drive clock frequency of the integrated circuit. This reduces power consumption and dissipation until the integrated circuit cools and the heat sink core solidifies.

Abstract: An integrated circuit device including a substrate, a gate structure formed over the substrate, a channel formed in the substrate under the gate, a lightly-doped drain-side LDD region formed in the substrate adjacent to a drain-side of the channel (preferably by a LATID process), a drain region formed in the substrate near to the drain-side LDD region, and a drain-side DDD region substantially separating the drain-side LDD region from the drain region. Preferably, the integrated circuit device is symmetrically formed such that a lightly-doped source-side LDD region is formed in the substrate adjacent to a source-side of the channel (again preferably by a LATID process), a source region is formed in the substrate near to the source-side LDD region, and a source-side DDD region is formed in the substrate to substantially separate the source-side LDD region from the source region. Further preferably, the DDD regions substantially isolate the source and drain from a bulk portion of the substrate.

Abstract: A distributed I/O device monitoring logic for power management control. The distributed I/O device monitoring logic reduces the gate count of convention device monitoring logic since the decode logic does not exist at two locations in the system. The distributed I/O device monitoring logic also has the benefits of self configuring monitor circuits, improved functionality, and decreased system power management overhead. The distributed I/O device monitoring logic comprises peripheral control for monitoring an I/O address range of at least one I/O device and for detecting access to the I/O device; system controller means coupled to the peripheral control for providing a ready (RDY #) signal and a system management interrupt (SMI #) signal; and central processing unit (CPU) coupled to the peripheral control and the system controller means for receiving the RDY # signal and the SMI # signal from the system controller and for sending information to both the system controller and the peripheral control.

Abstract: A computer-aided design system for compacting an integrated circuit layout with standard cell components is described. A data receiving device is used to process an integrated circuit layout that includes standard cell components. The integrated circuit layout is characterized by a circuit layout database with a cell table defining a set of cells that represent all spaces in the integrated circuit layout. The cell table includes connector cell data to indicate whether a cell forms a portion of a connected group of cells. The system includes an adjustment mechanism to align internal connectors of a standard cell with a routing grid associated with the integrated circuit layout. The system also includes a movement mechanism to position right-edge external connectors of a standard cell at a uniform routing grid coordinate position. The system uses the connector cell data to identify a power bus and a ground bus of each standard cell.

Abstract: A power usage simulator generates, for all the logic cells in a circuit cell library, a power model that characterizes a cell's power consumption behavior as a two-part, piecewise-linear function based on signal slew rates and output load. A logic simulator is modified so that for each signal transition in a specified logic circuit, the logic simulator performs a power usage computation utilizing the power usage model for all cells affected by each signal transition. The power usage value for each signal transition is posted to a power usage output data structure, with each posted power usage value having an associated time value. The posted power usage values are then analyzed by (A) accumulating the posted power usage values to provide a total power usage value, and (B) clocking the accumulation of power usage values with an end user set clock rate so as to produce a power usage profile indicating the time varying rate of power consumption during the simulation time period.

Abstract: A block compiler system that allows a user to specify the total number of words and bits per word in a memory structure and to choose among alternative memory structures according to a user-selected criterion. In operation, the system varies the partitioning of memory address lines among column address lines and row address lines. Further, the system varies the internal memory structure according to a selected partitioning of memory address lines among column address lines and row address lines, and optimizes the memory structure based upon higher-level user-selected criteria.

Abstract: In a dry non-isotropic etching process, backside cooling by helium controls the rate and uniformity of etching in a thermal silicon layer, the taper of profiles etched into silicon dioxide layers, and the dimension and uniformity of etched structures in a polycide or polysilicon layer, on the surface of a silicon wafer. Helium pressures from greater than 2 torr to more than 10 torr are satisfactorily utilized to produce these effects.

Abstract: A multi-layered, high performance integrated circuit package is disclosed having a number of design features which increase the performance and manufacturability of the integrated circuit package, and reduce the effects of parasitic noise generated within the package. The metallic layers connecting contact fingers formed on ledges around the periphery of a die cavity area, to their respective package pins are organized such that a ground metallic layer is interposed between each pair of input/output signal metallic layers, and each input/output signal metallic layer is sandwiched between a pair of metallic layers wherein one layer of the pair is connected to a voltage supply and the other layer of the pair is connected to a corresponding ground reference.

Abstract: An apparatus and method for verifying a semiconductor process model. The apparatus consists of an atomic force microscope (AFM), a semiconductor process model and a model updater. The AFM measures an actual cross sectional profile of a submicron semiconductor device feature created by an IC processing step which could be photolithography. The semiconductor process model predicts the feature's cross sectional profile under a set of model conditions specified to match the actual conditions under which the IC processing step took place. The semiconductor process model is driven by a set of model parameters that relate feature profiles to processing conditions and details of the processing step being modelled. The model updater adjusts, if necessary, the model parameters of the semiconductor process model so that the predicted profile more closely approximates the actual cross sectional profile.

Abstract: Spin-on glass etchback is a technique commonly used to planarize the surface of a semiconductor wafer during fabrication. The etch rate of spin-on glass is largely affected by the amount of oxide exposed during the spin-on glass etchback process. The amount of oxide exposed during spin-on glass etchback is dependent upon the underlying pattern density of topography. A method of standardizing the pattern density of topography for different layers of semiconductor wafers to improve the spin-on glass etchback process used to planarize the surface of a wafer during processing is disclosed. In order to achieve a standardized pattern density of topography on the surface of a wafer, dummy raised areas are added into gaps between active conductive traces on a trace layer. In some embodiments, the standardized pattern density is in the range of approximately 40% to 80%.

Abstract: A method and process for reducing edge-related defects. The present invention comprises the steps of calibrating multiple process units such that the multiple process units are equally referenced with respect to an edge of a semiconductor wafer. The calibrated multiple process units are then utilized to precisely control respective termination distances of deposited substrate layers with respect to the edge of the semiconductor wafer. Furthermore, the deposited substrate layers are selectively stacked in manner which prevents semiconductor wafer edge-related defects. In so doing, the present claimed invention increases semiconductor device yields.

Abstract: The present invention provides a CMOS integrated circuit in which core transistors are provided with punch-through pockets, while the input/output transistors are not provided with punch-through pockets. Punch-through protection for the input/output transistors by virtue of their larger dimensions. The pockets, like lightly doped drains, are formed after the gates are formed but before the formation of gate sidewalls. However, the input/output are masked during the punch-through implants, but are unmasked for at least one of the lightly doped drain implants. The absence of pockets on the input/output transistors enhances their ESD resistance, and thus the ESD resistance of the incorporating integrated circuit.

Abstract: A dynamic arbitration system for controlling the data transfer between primary and secondary buses in a personal computer has master and target components on both buses. Primary and secondary bus arbiters are included in a bridge circuit, and initially operate independently of one another in a concurrent arbitration mode of operation. This avoids primary bus interruption for secondary-to-secondary transfers and optimizes the primary bus bandwidth. Whenever a secondary-to-primary bus data transfer cycle is detected, the bridge circuit switches the primary and secondary bus arbiters to an interlocked mode of operation. The interlocked arbitration mode of operation is maintained until the next secondary-to-secondary cycle is detected; whereupon the bridge circuit causes the primary and secondary bus arbiters to be switched back to the concurrent arbitration mode of operation.

Abstract: A method for predicting circuit interconnect delays in circuits of the type that have a driving device attached to an input node of a network having a plurality of nodes, with the driving device changing states from time to time so as to impose on the network a voltage different from the previous voltage of the network. The method includes the steps of estimating the waveform on the input node and predicting the waveforms on other nodes of the network on the basis of the estimated input node waveform.

Abstract: A phase locked loop including a VCO having a multi-stage oscillator portion and a combinational logic portion. The multi-stage oscillator portion is configured to oscillate at a VCO clock frequency during a steady state condition under the control of a VCO control signal, and is further operative to develop a plurality of clock phases at the VCO clock frequency, with one of such clock phases used in the determination of the VCO control signal. The combinational logic portion is responsive to at least some of the plurality of clock phases and is operative to combine clock phases to create an output clock having an output clock frequency that is a multiple of the input clock frequency.

Abstract: A secure mode within a dual mode processor is implemented. In a general/external mode, the dual mode processor executes instructions provided from an external source. The instructions are supplied to the processor via input/output to the processor. Upon receiving a special software or hardware interrupt, the dual mode processor enters a secure/internal mode. The interrupt specifies a secure function stored in a read-only memory within the dual mode processor. Upon receiving such an interrupt, input/output to the dual mode processor is disabled. The identified secure function is executed by the processor. During execution of the secure function, any attempt to insert instructions not originating from the read-only memory are ignored. However, the processor may access data specifically identified by secure function being executed.

Abstract: A computer-aided design method and apparatus for compacting semiconductor circuit layouts to meet a specified set of design rules begins by fracturing a specified circuit layout into a set of trapezoids and storing the resulting cells in a database identifying the boundaries of each cell, and the cell adjacent each boundary. Nonempty cells are identified as being of specific materials, and empty spaces between cells are represented in the database. For each cell boundary, the database also stores data representing the boundary edge's end points. Neighboring cells on the same and related layers of the circuit layout share edges in the database. When a point on an edge of a cell is moved, the edge of each neighboring cell that shares that point is also moved. However, the method sizes gate cells of transistors differently from other cells by maintaining the former at predetermined dimensions, with a user-definable override to resize transistors to a percentage of the predetermined dimensions.

Abstract: An inverter is connected between the control nodes of two transistors in a current mirror system which forms a closed current feedback loop. Any difference between the bias voltages at the input and output of the inverter is reduced to zero. The self-biasing inverter amplifier may comprise the active part of an oscillator but may also be used as a level shifter or a reference circuit.

Abstract: A multi-purpose keyboard controller includes a matrix keyboard control circuit, a serial keyboard control circuit, a PC/AT port control circuit, and an external interface for RTC control. These control circuits are coupled in parallel with the interface logic of the computer system and use the built-in SMI interrupt mechanism of the computer system for reading and writing the keyboard or capturing keypress events. Software BIOS setup is employed to select one of the keyboard control circuits for utilization with the particular personal computer with which the system is employed. The interrupt scheme used by the keyboard interface uses SMI interrupts to the processor and SMI based software routines to read and write the values to and from the keyboard, thereby eliminating the need for dedicating a special hardware interrupt level; so that the system remains compatible with the DOS PC/AT Port 60/64h software interface.