Patents Assigned to Western Digital Technologies, Inc.
  • Patent number: 10389381
    Abstract: A decoder is configured to perform, for a unit of data received by the decoder, a plurality of decoding iterations in which a plurality of messages are passed between a plurality of check nodes and a plurality of variable nodes, each message indicating a degree of reliability in an observed outcome of data. The decoder determines, for each of the plurality of decoding iterations, whether a trigger condition is satisfied based on an internal state of the decoder and, when a trigger condition is determined to be satisfied during a respective decoding iteration, scales one or more respective messages of the plurality of messages during a subsequent decoding iteration. The unit of data is decoded based on the plurality of decoding iterations and at least one scaled message resulting from the trigger condition being satisfied during the respective decoding iteration.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kent D. Anderson, Anantha Raman Krishnan
  • Patent number: 10389580
    Abstract: A single-geo system includes a network configuration generator and a first computing system rack, or a multi-geo system includes a network configuration generator, a first computing system rack, and a second computing system rack are described. The system receives network information for a first plurality of nodes and a second plurality of nodes, and generates a system-wide network configuration file including network configuration information for the first plurality of nodes and the second plurality of nodes. Each plurality of nodes includes a controller node to receive the system-wide network configuration file, identify network configuration information for this plurality of nodes in the system-wide network configuration file as being part of the computing system rack, and update network configuration for this plurality of nodes based on the identified network configuration information for the computing system rack.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nina Tang, Ruben De Zaeytijd, Carl Rene D'Halluin
  • Patent number: 10388305
    Abstract: Disclosed herein are apparatuses and methods for writing to a magnetic medium, and data storage devices comprising such apparatuses and methods. An apparatus comprises a main pole, a trailing shield, a write-field-enhancing structure, a write coil, a write current control circuit configured to supply a write current to the write coil to record a bit to a magnetic medium, and a driving current control circuit configured to supply a driving current to the write-field-enhancing structure, wherein the driving current comprises a driving pulse. A method of writing to a magnetic medium comprises supplying a write current to a write coil of a magnetic write head, and supplying a driving current to a free layer disposed in a write gap between a main pole and a trailing shield of the magnetic write head, wherein the driving current comprises an AC component.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Gonçalo Marcos Baião De Albuquerque, Yunfei Ding, Alexander Goncharov, Kuok San Ho, Daniele Mauri, Goran Mihajlovic, Suping Song, Petrus Antonius Van Der Heijden
  • Patent number: 10388327
    Abstract: A sound-attenuation part, such as for use in a rack-mount server, is configured for insertion into an orifice of a backplane to which at least one data storage device is coupled. The sound-attenuation part may include one or more pipes extending from a mounting portion. The sound-attenuation part helps to attenuate acoustic noise, such as from a cooling fan, which might otherwise reach the data storage device, such as through airflow orifices constituent to a backplane that is positioned between the fan and the storage device, while maintaining enough airflow through the backplane for system cooling purposes. Thus, degradation of the head positioning accuracy within the storage device, caused by the forces associated with this acoustic noise, may be reduced.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Takehiko Eguchi, Miki Namihisa, Kazuhide Ichikawa, Yohei Asai
  • Patent number: 10387239
    Abstract: A computer-implemented method for detecting real flash failures in a runtime environment and determining the cause of the failure may include identifying a software parameter and a hardware parameter associated with a flash memory device at runtime; storing the software parameter and the hardware parameter in a failure detector module coupled to the flash memory device; detecting a flash translation layer failure associated with the flash memory device; performing analysis of the software parameter and the hardware parameter stored in the failure detector module by comparing them to predefined thresholds; and determining a cause of the flash translation layer failure based on the performed analysis.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Sateesh Kondapalli, Sri Rama Namala
  • Patent number: 10387303
    Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Pankaj Mehra, Vidyabhushan Mohan, Seung-Hwan Song, Dejan Vucinic, Chao Sun, Minghai Qin, Arup De
  • Patent number: 10387246
    Abstract: The subject technology provides for scanning blocks of a flash memory device for erased pages. A first codeword read from a page of a block in a flash memory device is received and provided to a first decoder for decoding. In response to receiving a first success indicator from the first decoder indicating that the first codeword was successfully decoded, first decoded data is provided from the first decoder to a second decoder for verification of the first decoded data. In response to receiving a first failure indicator from the second decoder indicating that the first decoded data was not verified, the page of the block is identified as being in an erased state based on the first success indicator received from the first decoder and the first failure indicator received from the second decoder.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Richard David Barndt, Seyhan Karakulak, Scott Kayser, Majid Nemati Anaraki, Anthony Dwayne Weathers
  • Patent number: 10389389
    Abstract: In an illustrative example, an apparatus includes a controller and a memory that is configured to store a codeword of a convolutional low-density parity-check (CLDPC) code. The codeword has a first size and includes multiple portions that are independently decodable and that have a second size. The controller includes a CLDPC encoder configured to encode the codeword and a CLDPC decoder configured to decode the codeword or a portion of the codeword.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Idan Goldenberg, Stella Achtenberg, Alexander Bazarsky, Eran Sharon, Karin Inbar, Michael Ionin
  • Patent number: 10387078
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller (such as a non-volatile memory (NVM) controller) to adaptively throttle the issuance of commands by a host to the controller. In illustrative examples, an NVM controller throttles the insertion of commands by the host into its submission queues to prevent timeouts that might otherwise occur if the NVM controller has slowed its operations (due, for example, to excessive temperatures within the NVM controller) and is thus unable to complete all issued commands within a host timeout interval. In some examples, throttling is achieved by providing the host with an adjusted head pointer set to a value to reduce the depth of the submission queue as observed by the host. Fewer commands are then sent by the host to the NVM controller via the submission queues, reducing the risk of a host timeout. NVMe examples are provided.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: August 20, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 10387081
    Abstract: Systems and methods for processing and arbitrating submission and completion queues are disclosed. NVM Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on the host device placing commands into the submission queue. The memory device processes the commands through various phases including fetching, processing, posting a completion message, and sending an interrupt to the host. The memory device may process the commands based on the determined priority of the command. For example, the memory device may determine a priority for performing the phases after fetching the command. As another example, the memory device may perform the internal command selection based on a priority associated with the command. In this way, commands may be executed based on the priority needs of the memory device or of the host device.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: Shay Benisty
  • Patent number: 10387226
    Abstract: A system on a chip or storage device has a dynamic process for handling system events that are transmitted at varying transmission rates. This dynamic process is a hybrid mode of operation that tailors the use of time stamp information according to the dynamic flow of events that are submitted in the system. Relative time stamps can be used along with explicit time stamps. Periodic wrap around events which use relative time stamps based on the periodic wrap events may be suppressed when there were no events between consecutive wrap around events. When an asynchronous event occurs during the suppression, the event is identified with a high precision time stamp (HPTS) rather than a relative time stamp. The periodic wrap around events can be re-initiated after the HPTS event is stamped.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 20, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: David Brief, Arseniy Aharonov, Amir Rozen, Asaf Gueta
  • Publication number: 20190250850
    Abstract: Technology is described herein for operating non-volatile storage. In one aspect, a memory controller replaces an original data buffer pointer(s) to a host memory data buffer(s) with a replacement data buffer pointer(s) to a different data buffer(s) in the host memory. The original data buffer pointer(s) may be associated with a specific read command. For example, the original data buffer pointer(s) may point to data buffer(s) to which data for some range of logical addresses (which may be read from the non-volatile storage) is to be transferred by a memory controller of the non-volatile storage. The replacement data buffer pointer(s) could be associated with a different read command. However, it is not required for the replacement data buffer pointer(s) to be associated with a read command. The replacement data buffer pointer(s) may point to a region of memory that is allocated for exclusive use of the memory controller.
    Type: Application
    Filed: February 15, 2018
    Publication date: August 15, 2019
    Applicant: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Judah Gamliel Hahn, Alon Marcu, Ariel Navon, Alexander Bazarsky
  • Patent number: 10379903
    Abstract: A data storage device may be configured to use multiple task queues to schedule tasks. The multiple task queues may be configured based on an architecture of the data storage device. In some implementations, the multiple task queues may be used to organize tasks received from an access device. In other implementations, the multiple task queues may be used to identify tasks, and identification of the tasks may be associated with an order of execution of the tasks.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Yoram Rimoni
  • Patent number: 10379139
    Abstract: Systems and methods are disclosed for testing circuit modules. A system for testing a circuit module includes a test circuit board configured to interface with a host system, a standard connector implemented on the test circuit board and configured to be attachably coupled to the circuit module, a micro-backplane module configured to be attachably coupled to the circuit module and a micro-backplane module interface connector implemented on the test circuit board and configured to be attachably coupled to the micro-backplane module.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: August 13, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sohail Mallick, Dmitry Vaysman, Hyun Soo Kim, Brian Hokyee Tse, Hariharan Venkataramani
  • Patent number: 10379952
    Abstract: The disclosed technology can advantageously provide an efficient data recovery system including a plurality of storage nodes including a first storage node and a second storage node, and a storage logic that is coupled to the storage nodes and that manages storage of data on the storage nodes. The storage logic is executable to: receive a data set including data elements including a first set of data elements associated with the first storage node and a second set of data elements associated with the second storage node; generate a first parity of the data set, the first parity including a horizontal parity including a set of horizontal parity entries; and combine the data elements from the data set to produce a skipper parity including a set of skipper parity entries. Combining the data elements includes transforming a subset of the data elements from the data set using an invertible operation, the set of horizontal parity entries being different from the set of skipper parity entries.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: August 13, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Robert Eugeniu Mateescu, Cyril Guyot, Lluis Pamies-Juarez
  • Patent number: 10379953
    Abstract: A distributed object storage system has a monitoring agent and/or a maintenance agent configured to determine for each of a plurality of repair tasks the actual concurrent failure tolerance of a corresponding repair data object. The actual concurrent failure tolerance corresponds to the number of storage elements that store sub blocks of the repair data object and are allowed to fail concurrently.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: August 13, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Koen De Keyser, Frederik De Schrijver, Bastiaan Stougie
  • Patent number: 10379760
    Abstract: A data storage device is disclosed comprising a head actuated over a disk comprising a plurality of tracks. A first degradation metric is maintained for a first segment of a first track, wherein the first degradation metric indicates a degree of degradation for data recorded in the first segment. The first degradation metric is processed to select an access command from a plurality of access commands including a read command to read the first segment. The selected access command is executed to access the disk.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: August 13, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventor: David R. Hall
  • Patent number: 10379755
    Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 13, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jerry Lo, Dominic S. Suryabudi, Lan D. Phan
  • Patent number: 10379951
    Abstract: Techniques for distributing data in a distributed data storage system using a hierarchy rule that is generated based on a spreading policy and a set of tolerable failures specified by a user in absence of system deployment information are disclosed. The system includes a controller node which receives a request including a spreading policy and a protection level for spreading a first data object. The controller node determines a hierarchy rule corresponding to the spreading policy based on the protection level. The controller node distributes the first data object in the system using the hierarchy rule and the spreading policy. The controller node receives a reconfiguration of system deployment. The controller node distributes a second data object in the system based on providing protection of the protection level to the second data object without affecting protection of the same protection level applied to the first data object.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 13, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Koen De Keyser, Frederik Jacqueline Luc De Schrijver, Stijn Blyweert
  • Patent number: 10379979
    Abstract: A device that provides power fail handling using command suspension includes non-volatile memory circuits and a controller that is configured to determine that a power fail event has occurred. The controller is configured to determine, in response to the determination that the power fail event has occurred, which of the non-volatile memory circuits are executing a first type of memory commands. The controller is also configured to issue a stop command to the determined non-volatile memory circuits to stop execution of the first type of memory commands.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: August 13, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: YungLi Ji, Yuriy Pavlenko, Kum-Jung Song