Abstract: Technology for reading memory cells in three-dimensional memory having multiple tiers. The memory system erases the tiers within each block independently. Then, memory cells in the tiers are programmed by units such as word lines. The memory system determines one or more read parameters for the selected tier based on the programmed/erased states of the other tiers in the block. For example, the memory system may select read reference levels for the selected tier based on the programmed/erased states of the other tiers. In an aspect, the one or more read parameters are used to determine the set of reference voltages for a bit error rate estimation scan (BES).

Abstract: A memory system implemented on one or more die includes a power input line for the one or more die, a current detection circuit connected to the power input line such that the current detection circuit is configured to indicate whether current at the power input is greater than a reference current, and a control circuit connected to the power input line and the current detection circuit. The control circuit is also connected to a non-volatile memory structure comprising a plurality of non-volatile memory cells. The control circuit is configured to sense data from the non-volatile memory structure including lowering a voltage used during the sensing in response to the current detection circuit indicating that current at the power input line is greater than the reference current.

Abstract: According to the selected command format mode, the same opcode of existing commands will now be able to be sent using a new command format that will compress the large command and achieve the same functionality as the original large command. Examples of such include address compression, repeated fields, unnecessary known fields, etc. Instead of a long address being sent across the ASIC-NAND bus, the address sent over the bus will be represented using less bits with lower granularity. The controller will not send known repeated elements e.g. of the long address in the new format utilizing the compressed command such that the address can be transmitted only once instead of several times per each command. The new format will not include parts of the commands that are defined by the standard when it is possible to eliminate their transmission. The new command format will have two or more supported versions some of the commands, allowing introduction of new flexibility and improved performance of the device.

Abstract: Technology is disclosed for reading memory cells having threshold switching selectors. A sense amplifier may have a set of capacitors that may be used to exchange charge with a sense node connected to the selected word line. A capacitor may be used to pull excess charge from the sense node or to provide charge to the sense node. A control circuit drives a current to the selected word line to charge up the selected word line to switch on the threshold switching selector of the selected memory cell. A capacitor may be connected to the selected word line when, or soon after, the threshold switching selector switches on. The capacitor may draw away excess charge to prevent a snapback current from flowing through the memory cell thereby preventing mis-reads. The capacitor may reduce read latency by speeding the rate of voltage change on a word line.

Abstract: In addition to transmitting over the ASIC-NAND bus the legacy long command format, a data storage device will be able to use also a compressed/improved command format. The alternate command's format is hidden from most parts of the NAND. The NAND can have a layer that will translate compressed/non standard commands to the legacy (standard) format for use by the rest of the NAND device's logic, as currently implemented. According to selected command format, the Low Level Flow Sequencer (LLFS) sequence generator and the flash interface module (FIM) will know which format to use in order to encode the command's content for transmission to the NAND by the FIM/ASIC/controller. The command is then executed on the NAND side according to the selected command scheme. Changes will be applied in the device controller on the ASIC side—to encode the command, and on the NAND side—to decode the command according to the selected format.

Abstract: Instead of using trees to group key values (KV) based on KV information, use host provided information for grouping KVs. In the cases where the host provides KV information, the host determines how to group the information. The controller will then use the KV information to store the KV information in a group. The KVs can be sorted in the group by either size, length, type, etc. of the KV received from the host. Independent backend logic, such as data routing management, parity management, block management, and proactive data retrieval, is used to group KV information. Grouping the KV information using the independent backend logic will make garbage collection (GC) less difficult and increase retrieval performance due to the grouping of the KVs.

Abstract: Different operations have different clock rate bottleneck points. For example, during a read operation, the processors may be the bottleneck whereas other operations will not be bottlenecks. Those other operations can have their clock rates reduced to save power since there is no benefit to a higher clock rate as the bottleneck is elsewhere. Predicting the bottleneck would be beneficial. Statistics correlating the bottleneck points with the workload and clock rates are tracked. When the workload changes, the statistics can be consulted to determine where the bottleneck is located and then slow down the clock rates for the non-bottleneck operations. A clock rate table is maintained in the device controller. The table holds the clock rate of each component. Predicting the workload and hence, the clock rates, reduces power consumption, improves performance, and better quality of service (QOS) compatibility characteristics.

Abstract: Technology is for managing non-volatile memory such as NAND memory. A memory system that programs the threshold voltages (Vt) of transistors on NAND strings to enable selection of sub-blocks without physically separate select lines in a block. A first set of one or more transistors on a NAND string may be programmed to a higher Vt and a second set of one or more transistors on the NAND string may be programmed to a lower Vt. Each NAND string in a sub-block may have the same pattern of high Vt and low Vt transistors. However, each sub-block has its own pattern of high Vt and low Vt transistors to enable selection of the sub-blocks. To select NAND strings in a sub-block, a high voltage is applied to a first set of the conductive lines and a low voltage is applied to a second set of the conductive lines.

Abstract: Various apparatuses, systems, methods, and media are disclosed to provide a heat-assisted magnetic recording (HAMR) medium. The HAMR medium includes a substrate, a heat sink layer on the substrate, and a plurality of magnetic recording layers on the heat sink layer. The plurality of magnetic recording layers includes a first magnetic layer and a second magnetic layer disposed on the first magnetic layer. The second magnetic layer includes FePt—Ag—Cu—X, wherein X is a segregant comprising BN. The HAMR medium can use BN-based segregants to improve a thermal gradient of the HAMR medium for better areal density capability (ADC) and enable the use of a MgO underlayer with reduced thickness.

Abstract: Various illustrative aspects are directed to a data storage device, method, and one or more processing devices that are configured to: select a seek time model from a plurality of seek time models based at least in part on an operational characteristic of an access command, the operational characteristic relating to an off-track susceptibility of executing the access command; determine an access time for the access command using the selected seek time model; and select a next access command for execution based on the determined access time for the access command and determined access times for other ones of a plurality of access commands.

Abstract: A suspension assembly for a magnetic storage device. The suspension assembly includes a base plate, a load beam, and a flexure. A hinge of the load beam is configured to flex so that a distal end portion of the load beam moves relative to the base plate. The flexure includes a hinge portion and fixed portions adjacent the hinge portion. Each one of the fixed portions of the flexure includes a first layer and a second layer. The first layer is interposed between the second layer and the load beam. The hinge portion of the flexure includes the second layer but does not include the first layer. A thickness of the second layer of the hinge portion of the flexure is less than a thickness of the second layers of the fixed portions of the flexure.

Abstract: A data storage device comprises a disk; a head configured to read data from and write data to the disk; and a current balancer configured to receive a first voltage supply having a load limit and to receive a second voltage supply. The current balancer is further configured, to mitigate rotational vibration (RV) noise, to sample a first current IH5V drawn from the first voltage supply, to maintain a difference between the first current IH5V and a current balancer threshold parameter IThreshold to be at least twice a minimum peak current minCurrentLimitpk amount required for turn on of the current balancer (IH5V?IThreshold?2*minCurrentLimitpk), and to draw a second current from the second voltage supply to satisfy a part of a total load on the first voltage supply that exceeds the load limit.

Abstract: A data storage device and method for delaying execution of a host write command to perform an internal memory operation. In one embodiment, a data storage device is provided comprising a memory with single-level cell (SLC) blocks and multi-level cell (MLC) blocks, as well as a controller. The controller is configured to store, in a queue, a plurality of write commands received from a host, wherein each write command is associated with a timeout window; determine how long each of the plurality of write commands has been pending in the queue; and for each write command, delay execution of the write command within the write command's timeout window until the write command has been pending in the queue for a specified amount of time, wherein delaying execution of each write command provides the controller with time to perform a memory operation to increase an amount of available SLC blocks in the memory. Other embodiments are provided.

Abstract: Various aspects are directed to a data storage device comprising one or more disks, an actuator mechanism configured to position a selected head among one or more heads proximate to a corresponding disk surface among the one or more disks, and one or more processing devices. The one or more processing devices are configured to detect repeatable runout (RRO) noise components from a measurement of fly height of the selected head above one or more sectors of a fly height measurement track, and remove the detected RRO noise components from one or more per-sector readback signal measurements.

Abstract: A data storage device comprises a lead actuator that actuates a first read-write head over a first disk and a support actuator that actuates a second read-write head over a second disk. A spindle motor rotates the first and second disks. In response to an emergency power off (EPO) event, a processing device retracts and parks the actuators using an internal supply voltage generated from a back electromotive force (BEMF) voltage of the spindle motor, and brakes the spindle motor. The spindle motor is not braked until both the lead and support actuators have been retracted and parked.

Abstract: A non-volatile memory comprises a plurality of non-volatile memory cells positioned in different regions of a block of non-volatile memory cells. Each region is connected to a different separate and independently controlled selection line so that each of the regions can be selected (e.g., one at a time) for a memory operation. To perform a read operation, the memory system is configured to apply a voltage to a selected word line and sequentially sense data from non-volatile memory cells positioned in the different regions without recharging the voltage applied to the selected word line.

Abstract: A transmitter controls the fall time on an open-drain link including multiple components. The transmitter includes an input driver to receive data and transmit the data on the open-drain link, thereby activating the open-drain link. The transmitter also includes a feedback mechanism to keep track of a pad when the open-drain link is activated and to determine when the pad reaches a predetermined amount of a supply voltage. When the pad reaches the predetermined amount of a supply voltage, the feedback mechanism triggers an appropriate main pull-down driver to control the fall time.

Abstract: Embodiments disclosed herein are directed to performing a single-side gate-induced drain leakage (GIDL) erase operation. Control circuitry may be configured to perform a single-side GIDL erase operation on a memory block in which a selected sub-block is erased while an unselected sub-block is not erased. During the single-side GIDL erase operation, the control circuitry may be configured to apply a first unselect bias voltage to a first set of word lines of the unselected sub-block, where the first set of word lines is associated with a first word line zone and the first word line zone is associated with an unselect bias voltage, and apply a second unselect bias voltage to a second set of word lines of the unselected sub-block, where the second set of word lines is associated with a second word line zone and the second word line zone is associated with another unselect bias voltage.

Abstract: A storage device processes deferred unmap operations while maintaining instructions in a write command. A controller in a storage device receives an unmap command and a write command from a host, determines that a logical page in the write command overlaps with a range in the unmap command with deferred unmap operations, and processes the write command. In processing the write command, an L2P translation manager sets a collision bit for the logical page and updates a L2P table. When processing the deferred unmap operations, the controller selects the range and if, based on collision bits in the range the controller determines that there is no overlap between the write command and the range, the controller performs the deferred unmap operations for the range. If the controller determines that there is an overlap, the controller processes the deferred unmap operations to not override the write command.

Abstract: A storage device minimizes HPB entry inactivation resulting from data associated with hot reads being retrieved from multiple HPB sub-regions covering a logical-to-physical table. The storage device may support the HPB feature and a multiple HPB sub-region mode. The storage device includes a controller that tracks a hit count associated with a logical block address in a read command. The controller determines that the hit count has reached a hit threshold and updates a hit table to identify logical block address pages associated with hit counts that have reached the hit threshold across HPB sub-regions covering a logical-to-physical table. The controller transmits the hit table to a host device to be stored in an HPB cache on the host device and to be used by the host device for read commands sent from the host device to the storage device.