Patents Assigned to Western Digital Technologies, Inc.
  • Publication number: 20220245242
    Abstract: An apparatus, system, and method for detecting compromised firmware in a non-volatile storage device. A control bus of a non-volatile storage device is monitored. The non-volatile storage device includes a processor and electronic components coupled to the control bus. Signal traffic on the control bus is analyzed for events and/or triggers related to storage operations initiated on the control bus by the processor. Storage operations include one or more commands directed to at least one of the electronic components. If the latency for the storage operation satisfies an alert threshold a host is notified of compromised firmware.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Judah Gamliel HAHN, Shay Benisty, Ariel Navon
  • Patent number: 11404632
    Abstract: Magnetoelectric or magnetoresistive memory cells include a magnesium containing nonmagnetic metal dust layer located between a free layer and a dielectric capping layer.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: August 2, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Bhagwati Prasad
  • Patent number: 11404080
    Abstract: The present disclosure generally relates to a magnetic media drive employing a magnetic recording head. The magnetic recording head comprises a first write head and a second write head each coupled to a first pad and a second pad of a slider pad and an electrical circuit coupled to the first and second pads. The first write head is a wide writing write head, and the second write head a narrow writing write head. The electrical circuit comprises a first sub-circuit and a second sub-circuit connected in parallel. The first sub-circuit comprises a capacitor and a connection to a first thermal fly height control (TFC) of the first write head. The second sub-circuit comprises an inductor and a connection to a second TFC of the second write head. The electrical circuit is further connected to a third TFC of a read head, the second write head comprising the read head.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: August 2, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quang Le, Jih-Shiuan Luo, Thao A. Nguyen, Kuok San Ho
  • Patent number: 11403252
    Abstract: A method and apparatus are provided to receive a voltage at a first value at a voltage reducing adaptor, ascertain a voltage supply requirement for the memory arrangement to obtain and ascertained voltage supply requirement, reduce the voltage from the first value to the ascertained voltage supply requirement within the adaptor and supply the voltage at the ascertained voltage supply requirement to the memory arrangement.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: August 2, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Charles Neumann, Robert P. Ryan
  • Patent number: 11404079
    Abstract: A data storage device is disclosed comprising a head actuated over a magnetic media. A write operation is executed to a first data sector by writing to at least part of a defective data sector preceding the first data sector in order to achieve a target fly height of the head prior to writing to the first data sector.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: August 2, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Joey M. Poss, Naoto Ito, Phillip S. Haralson
  • Patent number: 11403176
    Abstract: A system, method and apparatus for storing metadata in a metadata store in a robust and efficient manner including receiving a request from a client to perform a data transaction, updating a key-value pair in a metadata store based on the request, entering the data transaction in a transaction log, updating a read cache with the key-value pair, and replicating the last transaction log entry in at least one other storage node in the metadata store.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 2, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Frederik Jacqueline Luc De Schrijver, Joris Custers, Carl Rene D'Halluin
  • Patent number: 11403269
    Abstract: Example distributed storage systems, replication managers, and methods provide versioning validation for data transfers between heterogeneous data stores. A first object data store includes a versioned data object with a plurality of sequential versions corresponding to the versioned data object. A versioned write request message is sent to a second object data store and a response is received. The versioning-enabled status of the second object data store is determined from the response message and, if the versioning enabled status is invalid, any residual object versions in the second object data store are deleted based on a delete request.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 2, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomy Ammuthan Cheru, Vibhor Arunkumar Patale
  • Patent number: 11403163
    Abstract: A storage system and method for crash analysis are provided. In one embodiment, a storage system comprises a memory and a controller. The controller is configured to store a crash log in a buffer in the controller; determine whether the storage system has crashed; and in response to determining that the storage system has crashed, send the crash log from the buffer in the controller to a host in communication with the storage system. Other embodiments are provided.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: August 2, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Abhishek Shetty
  • Patent number: 11404193
    Abstract: Magnetoelectric or magnetoresistive memory cells include a magnesium containing nonmagnetic metal dust layer located between a free layer and a dielectric capping layer.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: August 2, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Bhagwati Prasad
  • Patent number: 11403529
    Abstract: The system described herein can include neural networks with noise-injection layers. The noise-injection layers can enable the neural networks to be trained such that the neural networks are able to maintain their classification and prediction performance in the presence of noisy data signals. Once trained, the parameters from the neural networks with noise-injection layers can be used in the neural networks of systems that include resistive random-access memory (ReRAM), memristors, or phase change memory (PCM), which use analog signals that can introduce noise into the system. The use of ReRAM, memristors, or PCM can enable large-scale parallelism that improves the speed and computational efficiency of neural network training and classification. Using the parameters from the neural networks trained with noise-injection layers, enables the neural networks to make robust predictions and calculations in the presence of noisy data.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: August 2, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Minghai Qin, Dejan Vucinic
  • Patent number: 11402884
    Abstract: A crossflow air deflector part for directing airflow includes a front central spine, a first arcuate wall extending from the spine to a first back lateral edge of the airflow deflector, and a second arcuate wall extending from the spine to a second back lateral edge of the airflow deflector opposing the first back lateral edge. Such an airflow deflector can be implemented into a storage server, positioned between a laterally adjacent pair of data storage device (DSD) chambers and a pair of vertically stacked fans, such that the crossflow air deflector functions to direct airflow from one of the lateral DSD chambers into the lower fan and to direct airflow from the other lateral DSD chamber into the upper fan. Independent airflow control for each DSD chamber and each corresponding DSD is thereby provided.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: August 2, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shailesh R Nayak, Joe Paul Moolanmoozha, Steven Cheng, Erik Silaprasay, Nicholas Maris
  • Patent number: 11403011
    Abstract: Aspects of a storage device including a memory and a controller are provided. The memory includes a volatile memory. The controller can determine that at least a portion in the volatile memory is a reusable region based on a host memory allocation from a host device. The controller also can calculate a size of the reusable region in the volatile memory. The controller also can perform one or more storage device operations in the reusable region of the volatile memory in response to the host memory allocation based on the calculated size of the reusable region. Thus, the controller may provide smart handling of host memory buffer allocation, thereby improving storage device read performance.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: August 2, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Sridhar Prudvi Raj Gunda, Santhosh Kumar Siripragada
  • Publication number: 20220236919
    Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
    Type: Application
    Filed: April 11, 2022
    Publication date: July 28, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Amir Shaharabany, Eliad Adi Klein
  • Publication number: 20220238135
    Abstract: A magnetic head includes a main pole configured to serve as a first electrode, an upper pole containing a trailing magnetic shield configured to a serve as a second electrode, and an electrically conductive portion located in a trailing gap between the main pole and the trailing magnetic shield. The electrically conductive portion is not part of a spin torque oscillator stack, and the electrically conductive portion includes at least one electrically conductive, non-magnetic material layer. The main pole and the trailing magnetic shield are electrically shorted by the electrically conductive portion across the trailing gap between the main pole and the trailing magnetic shield such that an electrically conductive path is present between the main pole and the trailing magnetic shield through the electrically conductive portion.
    Type: Application
    Filed: April 14, 2022
    Publication date: July 28, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Zhigang BAI, Youfeng ZHENG, Venkatesh CHEMBROLU, Supradeep NARAYANA, Yaguang WEI, Suping SONG, Terence T. LAM, Kuok San HO, Changqing SHI, Lijie GUAN, Jian-Gang ZHU
  • Patent number: 11398246
    Abstract: The present disclosure relates to pretreating a magnetic recording head for magnetic media drive. For a heat assisted magnetic recording (HAMR) head, a light source provides the necessary heat for the drive to operation. A vertical cavity surface emitting laser (VCSEL) is mounted to a top surface of a slider. A plurality of laser beams are emitted from the bottom surface of the VCSEL and directed to a corresponding number of waveguide structures within the HAMR head. The waveguide structures feed into a multimode interference (MMI) device that then directs the laser into a single waveguide for focusing on a near field transducer (NFT). The VCSEL lasers are phase coherent and have no mode hopping.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: July 26, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Barry Stipe, Takuya Matsumoto, Sergei Sochava
  • Patent number: 11397460
    Abstract: For solid state drive (SSD) or other memory system formed of multiple memory dies, techniques are presented for operation in a standby mode with increased power savings. The memory dies are operable in a regular standby mode and in a low power standby mode. Based upon the amount of current each of the memory dies in the regular standby mode, when the device goes into standby the memory dies that draw higher amounts of current when in the regular standby mode are instead placed into the low power standby mode. The amount of current drawn by each of the memory die in the regular standby mode can be determined for each of the memory dies at die sort or as part of the memory test process, or can be determine by an assembled SSD itself.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 26, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Nian Niles Yang, Dmitry Vaysman, Ekram Bhuiyan
  • Patent number: 11398247
    Abstract: Magnetic recording media including a soft magnetic underlayer (SUL) formed over an oxidized pre-seed layer. In some examples, the pre-seed layer is oxidized to reduce an amount of intermixing between the pre-seed layer and the SUL. The reduction in intermixing via oxidation can lead to improved recording performance of the recording media that are deposited on the SUL. In particular, media overwrite, signal-to-noise ratio (SNR), linear recording density, and areal recording density or areal density capacity (ADC) can be improved. In one aspect, a deposition apparatus may be modified to inject oxygen during pre-seed layer deposition to oxidize the pre-seed layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: July 26, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Kai Tang
  • Patent number: 11397699
    Abstract: A data storage device, such as a solid state drives (SSD), includes command completion interrupt coalescing. A controller of the data storage device includes one or more completion queues, each including interrupt coalescing protection logic. The interrupt coalescing protection logic detects that a head pointer or a tail pointer in a completion queue has not changed for a predetermined period of time. When the head and tail pointers have not changed for the predetermined period of time, the controller posts an interrupt to a host device.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: July 26, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Publication number: 20220229555
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
    Type: Application
    Filed: February 24, 2021
    Publication date: July 21, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Rotem Sela, Einav Zilberstein, Karin Inbar
  • Publication number: 20220229731
    Abstract: A storage system comprises a non-volatile memory configured to store boot code and a control circuit connected to the non-volatile memory. In response to a first request from a host to transmit the boot code, the storage system commences transmission of the boot code to the host at a first transmission speed. Before successfully completing the transmission of the boot code to the host at the first transmission speed, it is determined the boot code transmission has failed. Therefore, the host will issue a second request for the boot code. In response to the second request for the boot code, and recognizing that this is a fallback condition because the previous transmission of the boot code failed, the storage apparatus re-transmits the boot code to the host at a lower transmission speed than the first transmission speed.
    Type: Application
    Filed: June 6, 2021
    Publication date: July 21, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yoseph Pinto, Rampraveen Somasundaram