Abstract: A programmable switch includes ports configured to communicate with Non-Volatile Memory express (NVMe) nodes. The programmable switch is configured to store a mapping of NVMe namespaces to physical storage locations located in the NVMe nodes. An NVMe node is determined by the programmable switch to have become inactive, and one or more NVMe namespaces are removed from the mapping that are associated with one or more physical storage locations in the inactive NVMe node. A notification of the one or more removed NVMe namespaces is sent to a network controller. According to one aspect, the network controller stores a global mapping of NVMe namespaces to physical storage locations in the NVMe nodes. The network controller sends at least one notification of the update to at least one other programmable switch to update at least one mapping stored at the at least one other programmable switch.

Abstract: The present disclosure generally relates to a tape drive comprising one or more tape head modules. Each tape head module comprises a chip and a beam, such as a u-beam. Each chip comprises a first data element array and a second data element array, where each data element array comprises 33 write elements or 33 read elements and one or more servo element pairs. Each data element of both the first and second data element arrays is coupled to two pads. The pads and the data element arrays of each chip are offset in a first direction such that the pads and data element arrays are offset from a central axis a distance about one-half the span of either the first or second data element array. Either the first data element array or the second data element arrays is centered upon the central axis.

Abstract: Various apparatuses, systems, methods, and media are disclosed for heat-assisted magnetic recording (HAMR) that, in some examples, provide a HAMR medium with two soft underlayers (SULs) on opposing sides of a single heatsink layer. For example, a magnetic recording medium is provided that includes a lower SUL on a substrate. The lower SUL is configured and positioned within the medium to provide a first return path for magnetic flux from a magnetic recording head during a write operation. The medium also includes a heatsink layer on the lower SUL and an upper SUL on the heatsink layer. The upper SUL is configured and positioned within the medium to provide a second return path for magnetic flux from the magnetic recording head. A magnetic recording layer is provided on the upper SUL to store information during the write operation. Additional layers or films may be provided as well.

Abstract: A process of assembling a voice coil motor (VCM), such as for a hard disk drive, includes creating an opening in a yoke, attaching a primary magnet to an inside surface of the yoke, installing through the opening in the yoke a cross-flux magnet into a channel of the primary magnet, and installing a plug into the opening in the yoke. Thus, part count is minimized and the manufacturing process is readily incorporated into existing VCM manufacturing processes.

Abstract: Aspects of the disclosure are directed to a storage device including a memory and a controller. In some examples, the controller is configured to measure an error rate of one or more blocks of the memory. In some examples, the controller is further configured to estimate, based at least in part on the error rate, a time shift indicative of a duration of time for which the storage device was powered off. In some examples, the controller is further configured to set a read level for multiple blocks of the memory, wherein the read level is determined based at least in part on the time shift.

Abstract: A data storage device and method for host-assisted improved error recovery using a correlation factor are provided. In one embodiment, the data storage device receives, from a host, an indication that data associated with a first logical address is correlated with data associated with a second logical address; determines a correlation factor based on a degree of correlation between the data associated with the first logical address and the data associated with the second logical address; and in response to the correlation factor being above a threshold: stores the data associated with the first logical address and the data associated with the second logical address in different regions of the memory having different bit error rates; and uses the data associated with the first logical address to assist in correcting an error in the data associated with the second logical address. Other embodiments are provided.

Abstract: A data storage device and method are provided for selecting a data recovery mechanism based on a video frame position. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to retrieve a video frame stored in the memory; detect an error in the video frame; and select how to handle the error based on a position of the video frame in a group of pictures. Other embodiments are provided.

Abstract: A data storage device and method for host-assisted efficient handling of multiple versions of data are provided. In one embodiment, a data storage device is provided comprising a memory and a controller. The controller is configured to receive, from a host, identification of different versions of data that are to deleted together, store the different versions of the data in areas of the memory that are erasable in parallel; receive, from the host, a command to erase the different versions of the data; and erase the different versions of the data in parallel. Other embodiments are provided.

Abstract: A data storage device and method for enhanced recovery through data storage device discrete-component-hardware-reset are provided. In one embodiment, the data storage device determines that a subset of a plurality of memory dies is non-responsive, sends a request to a host to accept longer delays associated with the subset of the plurality of memory dies, power-cycles the subset of the plurality of memory dies, and then informs the host that the latency associated with those dies has been restored to normal latency or that the subset of the plurality of memory dies are inactive (in case of unsuccessful recovery). Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in memory holes coupled to bit lines. A control means successively applies each of a series of pulses of a program voltage to selected ones of the word lines while simultaneously applying one of a bit line program voltage and a bit line inhibit voltage to ones of the bit lines coupled to the memory holes containing groups of the memory cells connected to the selected ones of the plurality of word lines to program the groups of the memory cells with data. The control means maintains a voltage applied to ones of the plurality of bit lines as the bit line inhibit voltage in response to the ones of the plurality of bit lines remaining unselected when programming a next one of the groups of the memory cells.

Abstract: Technology is disclosed herein for programing memory cells with a post-program erase. In an aspect, the post-program erase includes a bit-level erase that only erases memory cells that are to remain in an erased state after the program operation. Memory cells that are to remain in programmed states may be inhibited from erase during the post-program erase. In an aspect, the post-program erase does not have an erase verify, which saves time and/or power. In an aspect, the post-program erase includes applying a single erase pulse, which saves time and/or power. In an aspect, the duration of the post-program erase pulse is shorter than an erase pulse used prior to programming, which saves time and/or power.

Abstract: Method for performing a memory operation with respect to a memory structure having “N”-number of planes, each plane comprising “M”-number of blocks and “X”-number of word lines arranged in a serial order, and electrically connected with each plane are: a voltage bias source, an electronic switching component, and row decoder, the method comprising: with respect to each plane, selecting a block and a word line for application of the operation, wherein the operation has not been applied to the selected block and word line, the selected block of one plane is located in a different block group from the selected block of another plane, and the selected word line of one plane is in a different position within the serial order from a position of the selected word line of another plane; and using the voltage bias source, concurrently applying the operation to the selected blocks and selected word lines.

Abstract: A data storage device comprises a first memory, a second memory, and a controller. The first memory has a faster access time than the second memory. The controller is configured to store host-initialization code in the first memory, store a copy of the host-initialization code in the second memory, determine that the copy of the host-initialization code should be designated as the main version of the host-initialization code, and relocate the copy of the host-initialization code to the first memory, which makes the copy of the host-initialization code the main version of the host-initialization code that is accessed to boot-up the host. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Systems, methods, and data storage devices for data recovery from network storage systems are described. The data storage device may include a host data channel for data transfer with the host and a network data channel for data transfer with the network storage system over a network. Responsive to a read error when reading a data unit, the data storage device establishes a secure data transfer connection with the network storage system to request the failed data unit from the network storage system. The data unit retrieved from the network storage system may be used to respond to the original read request and restore the data unit in the data storage device.

Abstract: The present disclosure generally relates to improved consolidation in dual-layer FTL. In preparation for the next control sync, the controller will generate a copy the uRegions uHeaders and will continue updating the uLayer uRegion with new uRun entries. After completing the control sync operation, the controller will then select the best consolidation candidate based on comparing the uRegion uHeaders with their copy and determining the uRegion with the maximum uRuns difference or the greatest number of uRun updates in case the uRun updates difference is less than a threshold. The controller then reads the selected mSets from the flash memory to its cache and merges the updated uRuns with the cached mSets.

Abstract: Jumboblocks (JBs) having an uncorrectable error correction code (UECC) error are linked to a bad block in a storage address table (SAT) in order to optimize read and write operations. Bad blocks are designated as a bad block during a manufacturing process or associated with a write uncorrectable error. When a JB is identified as having the UECC error, the controller updates a corresponding mapping of the SAT to point to a bad block, where each JB having the UECC error points to the bad block. When a read command is received by the controller for the data of the JB having the UECC error, the controller scans the SAT, determines, from the SAT, that the JB identification points to the bad block, and returns a UECC message to the requester of the data of the JB having the UECC error.

Abstract: The memory device includes a memory block with memory cells arranged in word lines and control circuitry that is configured to program the memory cells in a selected word line to respective programmed data states in program loops, which each include verify operations. The control circuitry is further configured to lock out any of the memory cells in the selected word line memory cell from subsequent program pulses and verify operations in response to that memory cell passing verify for its respective programmed data state. For a selected programmed data state, the control circuitry is further configured to re-verify all of the memory cells in the selected word line that are being programmed to the selected programmed data state and release all memory cells that were locked out but fail re-verify in order to allow any memory cells that mistakenly passed verify to be programmed further.

Abstract: A method for performing a programming operation with respect to a memory structure. The method comprises: (1) initiating a programming operation with respect to multiple program states of a non-volatile memory structure; (2) programming each of the multiple program states according to a programming order; and (3) after completing the programming of each of the multiple program states, programming an erase state as the final program state of the programming order.

Abstract: Various illustrative aspects are directed to a data storage device, comprising one or more disks; an actuator mechanism configured to position one or more heads proximate to a corresponding disk surface of the one or more disks; and one or more processing devices. The one or more processing devices are configured to generate a determination of magnetic responsiveness to thermal energy of at least one position of the corresponding disk surface in response to an operation of the selected head. The one or more processing devices are further configured to determine and apply a pre-bias current to the thermally energizing component prior to a write operation, with the selected head proximate to the at least one position of the corresponding disk surface, wherein the pre-bias current is based on the determination of magnetic responsiveness to thermal energy of the at least one position of the corresponding disk surface.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes each coupled to one of a plurality of bit lines. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to read the memory cells in a read operation. The control means is also configured to adjust at least one word line read timing and ramping parameter used during the read operation based on an amount of cycling of the memory cells.