Patents Assigned to Western Digital Technologies, Inc.
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Patent number: 11967388Abstract: Technology is disclosed herein for detecting grown bad blocks in a non-volatile storage system. A stress test may accelerate stressful conditions on the memory cells and thereby provide for early detection of grown bad blocks. The stress test may include applying a program voltage to a selected word line and a stress voltage that is less than a nominal boosting voltage to a word line adjacent one side of the selected word line. The combination of the program voltage and the stress voltage may generate an e-field that is stronger than an e-field that would be generated in a normal program operation, thereby accelerating the stress on the memory cells. The stress test mat further include programming all of the memory cells to a relatively high threshold voltage, which may create additional stress on the memory cells.Type: GrantFiled: August 11, 2022Date of Patent: April 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Sarath Puthenthermadam, Longju Liu, Parth Amin, Sujjatul Islam, Jiahui Yuan
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Patent number: 11966630Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to segment a key to physical (K2P) table into two or more segments, wherein each segment of the two or more segments corresponds to a caching priority of key value (KV) pair data, organize the K2P table by storing and relocating one or more K2P table entries into a respective segment of the two or more segments, wherein the storing and relocating comprises moving a K2P table entry based on the caching priority of the KV pair data into the respective segment having the caching priority, and utilize the K2P table to manage KV pair data stored in the memory device, wherein utilizing the K2P table comprises applying a same management operation, such as prefetching, to each K2P table entry of a same segment.Type: GrantFiled: June 27, 2022Date of Patent: April 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Ran Zamir, Alexander Bazarsky, David Avraham
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Patent number: 11966613Abstract: The present disclosure generally relates to reducing exit latency when transitioning from non-operational power states. Before entering a non-operational power state, specific data in databases and/or tables can be identified as being recently utilized by the host device. In addition to saving the databases and/or tables, a recovery code is also stored to identify that specific data. Upon transitioning back to an operational power state, the recovery code is detected and the specific data can be recovered rather than recovering the entire database and/or table. Data not identified in the recovery code need not be recovered from always-on memory. In so doing, when transitioning back to an operational power state, the latency will be reduced compared to a situation where all data is stored in always-on memory.Type: GrantFiled: November 24, 2021Date of Patent: April 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Shay Benisty, Nissim Elmaleh
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Patent number: 11966582Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists either in an input queue corresponding to a hardware module of a plurality of hardware modules or in the hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue or in the hardware module.Type: GrantFiled: August 10, 2022Date of Patent: April 23, 2024Assignee: Western Digital Technologies, Inc.Inventor: Refael Ben Rubi
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Patent number: 11966618Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The memory device is arranged into at least a first super device and a second super device, each of the super devices having a plurality of active zones. The controller is configured to determine that each of the super devices includes both cold zones and hot zones, where a cold zone is a zone that is overwritten less than a hot zone. The controller is further configured to move cold zones from one super device to another super device upon determining that the another super device is below a threshold limit, where the threshold limit is a minimum free space to be maintained in a super device. The controller is further configured to move cold zones between super devices, such that the cold zones are concentrated in at least one super device.Type: GrantFiled: August 25, 2021Date of Patent: April 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Ravishankar Surianarayanan, Matias Bjorling
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Patent number: 11968907Abstract: A magnetoresistive memory cell includes a first electrode, a second electrode that is spaced from the first electrode, a magnetic tunnel junction layer stack located between the first electrode and the second electrode, the magnetic tunnel junction layer stack containing, from one side to another, a reference layer having a fixed reference magnetization direction, a tunnel barrier layer comprising a dielectric material, and a free layer, and an asymmetric magnetoresistance layer located between the magnetic tunnel junction layer stack and one of the first electrode and the second electrode.Type: GrantFiled: July 5, 2022Date of Patent: April 23, 2024Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Goran Mihajlovic, Lei Wan
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Patent number: 11966626Abstract: In one example, a flash storage device includes a flash memory and a controller. The flash memory includes non-volatile memory cells organized into blocks. The blocks are switchable between multi-bit mode and single-bit mode for storing data. The blocks in single-bit mode have a lower storage density and a higher write endurance than the blocks in multi-bit mode. The controller is configured to receive a write request from a host, and to determine whether a trigger event has occurred to switch one or more of the blocks from multi-bit mode to single-bit mode. Based on the controller determining that the trigger event has occurred, the controller is further configured to switch the one or more blocks from multi-bit mode to single bit mode, and to store, in single-bit mode, data for the write request in the one or more blocks at the lower data storage density.Type: GrantFiled: May 13, 2022Date of Patent: April 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Ratan Singh Rathore, Ajay Shyam Manwani
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Patent number: 11966631Abstract: A method and system for maintaining command queue order are disclosed. According to certain embodiments, commands are read from a host, storing command queue IDs in an array that will keep the queue IDs in order. After having the queue IDs stored in the array, the commands are processed in the data storage device (DSD). After processing, the commands are provided to a completion order adjustment module that will order the commands in queue ID order for sequential commands to be returned to the host. In certain embodiments, for a sequential command, other commands of the same sequence are searched for the array and ordered with the sequential command. If a particular command of the sequence is not found, the completion order adjustment module will wait to transfer the sequence until each command of the sequence is found. For commands not part of a sequence, these commands are transferred to the host.Type: GrantFiled: April 16, 2021Date of Patent: April 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Sang Yun Jung, Min Woo Lee, Min Young Kim
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Publication number: 20240125687Abstract: A device may include a fluid region. A device may also include a magnetochemical sensor for detecting magnetic particles in the fluid region, wherein the magnetochemical sensor comprises: a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer situated between and coupled to the first ferromagnetic layer and the second ferromagnetic layer. A device may further include a current-carrying structure for drawing the magnetic particles in the fluid region toward the magnetochemical sensor, wherein: the current-carrying structure consists of a single, undivided structure, and the current-carrying structure is configured to carry a current in at least one direction that is substantially parallel to an in-plane axis or a longitudinal axis of the magnetochemical sensor. The magnetochemical sensor may be one of a plurality of magnetochemical sensors in a sensor array.Type: ApplicationFiled: July 14, 2023Publication date: April 18, 2024Applicant: Western Digital Technologies, Inc.Inventors: Daniel BEDAU, Alexander ELIAS
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Patent number: 11960741Abstract: The present disclosure generally relates to writing data to streams. A host device can instruct a data storage device to operate in implied streams mode such that the host device does not need to tell the data storage device the specific stream in which to write data. The data storage device would maintain a list of open append points of specific streams. Upon receiving a write command, the data storage device determines whether the write command is for an already open stream, and if so, write to the specific stream. If not, then the data storage device opens a new stream or write the data to an overflow stream.Type: GrantFiled: January 31, 2022Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Liam Parker, Matias Bjorling, Michael James
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Patent number: 11960766Abstract: A data storage device and method for accidental delete protection are provided. In one embodiment, a data storage device comprises a memory and a controller. The memory comprises a first set of physical blocks and a second set of physical blocks, where the first and second sets of physical blocks are associated with separate logical-to-physical address tables and/or separate block lists. The controller is configured to write data received from a host in the first set of physical blocks and move the data from the first set of physical blocks to the second set of physical blocks in response to the host requesting that a modified version of the data be written in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: GrantFiled: December 6, 2021Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Abhinandan Venugopal, Amit Sharma
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Patent number: 11960394Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To Utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.Type: GrantFiled: July 21, 2022Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Amir Shaharabany, Shay Vaza
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Patent number: 11960730Abstract: Systems and methods described herein synchronize events between various components of storage device during the processing of an exception (i.e., an internal error). The storage device can have a plurality of processors which may each coordinate operations on various domains of storage device processing tasks. An exception occurring in one domain may require input and coordination from other domains within the storage device. Each exception may have a list of predetermined steps needed for completion which are coordinated via a series of sync points placed between exception action clusters which perform a series of specific operations until data or processing from another domain is needed to continue processing. The sync points can be utilized to halt processing in one domain until the other domains are in sync and complete one or more exception action operations. In this way, a streamlined and predictable synchronization between domains may occur during an exception.Type: GrantFiled: June 28, 2021Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Rishi Mukhopadhyay, Shiva K
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Patent number: 11960395Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.Type: GrantFiled: July 21, 2022Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Amir Shaharabany, Shay Vaza
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Patent number: 11961542Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector with a first resistance, a resistance detection circuit electrically coupled to the first resistance and comprising a low and high frequency path corresponding to a DC and AC mode, respectively, and one or more processing devices configured to: bias the first resistance with a voltage bias, where the first resistance is coupled to a first and second amplifier, control a pulse generator to add a bias pulse on the HF path to generate a HF resistance detection signal, where the second amplifier is biased using the voltage bias and the bias pulse, control a clock to chop a LF signal at the first amplifier on the LF path, demodulate the chopped LF signal to generate a LF resistance detection signal, and concurrently process the HF and LF resistance detection signals.Type: GrantFiled: August 9, 2022Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: John Contreras, Joey M. Poss, Ronald Chang, Bernhard E. Knigge
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Patent number: 11960397Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.Type: GrantFiled: June 16, 2022Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Vered Kelner, Marina Frid, Igor Genshaft
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Patent number: 11960725Abstract: Embodiments of the present disclosure generally relate to an NVMe storage device having a controller memory manager and a method of accessing an NVMe storage device having a controller memory manager. In one embodiment, a storage device comprises a non-volatile memory, a volatile memory, and a controller memory manager. The controller memory manager is operable to store one or more NVMe data structures within the non-volatile memory and the volatile memory.Type: GrantFiled: December 7, 2022Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventor: Shay Benisty
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Patent number: 11961778Abstract: A semiconductor device package includes a substrate having a top planar surface and a first semiconductor die electrically connected to the top planar surface of the substrate. The first semiconductor die and substrate define a tunnel and a first molding compound encapsulates the first semiconductor die and fills the tunnel. A second molding compound that is separate and distinct from the first molding compound is mounted on a top surface of the first molding compound. The first molding, when in a flowable state, has a viscosity that is lower than a viscosity of the second molding compound when it is in a flowable state.Type: GrantFiled: September 27, 2021Date of Patent: April 16, 2024Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Shenghua Huang, Yangming Liu, Bo Yang, Ning Ye
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Patent number: 11960753Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The memory device includes at least a first super device and a second super device. Each of the super devices includes a plurality of active zones and a threshold value for a number of cold zones. The controller classifies zones as either a cold zone or hot zone depending the number of resets to the zone. If the number of resets to the zone is greater than a threshold reset value, then the zone is classified as a hot zone, otherwise the zone is classified as a cold zone. The controller is configured to determine that the number of cold zones is greater than the threshold value for a super device and move data from at least one cold zone from the super device to a zone of another super device.Type: GrantFiled: August 25, 2021Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Ravishankar Surianarayanan, Matias Bjorling
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Patent number: 11960758Abstract: Rather than use one long folding operation to fold data from single-level cell (SLC) blocks into a multi-level cell (MLC) block, a storage system uses a multi-stage folding operation. By breaking up the folding process into stages, SLC blocks involved in an earlier stage can be released prior to a subsequent stage being performed. This can increase performance of the storage system by releasing SLC source blocks sooner and reducing an SLC block budget requirement.Type: GrantFiled: April 6, 2022Date of Patent: April 16, 2024Assignee: Western Digital Technologies, Inc.Inventors: Bhanushankar Doni Gurudath, Harish Gajula