Abstract: A magnetoresistive memory cell includes a first electrode, a second electrode that is spaced from the first electrode, a magnetic tunnel junction layer stack located between the first electrode and the second electrode, the magnetic tunnel junction layer stack containing, from one side to another, a reference layer having a fixed reference magnetization direction, a tunnel barrier layer comprising a dielectric material, and a free layer, and an asymmetric magnetoresistance layer located between the magnetic tunnel junction layer stack and one of the first electrode and the second electrode.

Abstract: A method and system for maintaining command queue order are disclosed. According to certain embodiments, commands are read from a host, storing command queue IDs in an array that will keep the queue IDs in order. After having the queue IDs stored in the array, the commands are processed in the data storage device (DSD). After processing, the commands are provided to a completion order adjustment module that will order the commands in queue ID order for sequential commands to be returned to the host. In certain embodiments, for a sequential command, other commands of the same sequence are searched for the array and ordered with the sequential command. If a particular command of the sequence is not found, the completion order adjustment module will wait to transfer the sequence until each command of the sequence is found. For commands not part of a sequence, these commands are transferred to the host.

Abstract: In one example, a flash storage device includes a flash memory and a controller. The flash memory includes non-volatile memory cells organized into blocks. The blocks are switchable between multi-bit mode and single-bit mode for storing data. The blocks in single-bit mode have a lower storage density and a higher write endurance than the blocks in multi-bit mode. The controller is configured to receive a write request from a host, and to determine whether a trigger event has occurred to switch one or more of the blocks from multi-bit mode to single-bit mode. Based on the controller determining that the trigger event has occurred, the controller is further configured to switch the one or more blocks from multi-bit mode to single bit mode, and to store, in single-bit mode, data for the write request in the one or more blocks at the lower data storage density.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to segment a key to physical (K2P) table into two or more segments, wherein each segment of the two or more segments corresponds to a caching priority of key value (KV) pair data, organize the K2P table by storing and relocating one or more K2P table entries into a respective segment of the two or more segments, wherein the storing and relocating comprises moving a K2P table entry based on the caching priority of the KV pair data into the respective segment having the caching priority, and utilize the K2P table to manage KV pair data stored in the memory device, wherein utilizing the K2P table comprises applying a same management operation, such as prefetching, to each K2P table entry of a same segment.

Abstract: A device may include a fluid region. A device may also include a magnetochemical sensor for detecting magnetic particles in the fluid region, wherein the magnetochemical sensor comprises: a first ferromagnetic layer, a second ferromagnetic layer, and a spacer layer situated between and coupled to the first ferromagnetic layer and the second ferromagnetic layer. A device may further include a current-carrying structure for drawing the magnetic particles in the fluid region toward the magnetochemical sensor, wherein: the current-carrying structure consists of a single, undivided structure, and the current-carrying structure is configured to carry a current in at least one direction that is substantially parallel to an in-plane axis or a longitudinal axis of the magnetochemical sensor. The magnetochemical sensor may be one of a plurality of magnetochemical sensors in a sensor array.

Abstract: Various illustrative aspects are directed to a data storage device comprising a slider with a resistive temperature detector with a first resistance, a resistance detection circuit electrically coupled to the first resistance and comprising a low and high frequency path corresponding to a DC and AC mode, respectively, and one or more processing devices configured to: bias the first resistance with a voltage bias, where the first resistance is coupled to a first and second amplifier, control a pulse generator to add a bias pulse on the HF path to generate a HF resistance detection signal, where the second amplifier is biased using the voltage bias and the bias pulse, control a clock to chop a LF signal at the first amplifier on the LF path, demodulate the chopped LF signal to generate a LF resistance detection signal, and concurrently process the HF and LF resistance detection signals.

Abstract: Embodiments of the present disclosure generally relate to an NVMe storage device having a controller memory manager and a method of accessing an NVMe storage device having a controller memory manager. In one embodiment, a storage device comprises a non-volatile memory, a volatile memory, and a controller memory manager. The controller memory manager is operable to store one or more NVMe data structures within the non-volatile memory and the volatile memory.

Abstract: A data storage device and method for accidental delete protection are provided. In one embodiment, a data storage device comprises a memory and a controller. The memory comprises a first set of physical blocks and a second set of physical blocks, where the first and second sets of physical blocks are associated with separate logical-to-physical address tables and/or separate block lists. The controller is configured to write data received from a host in the first set of physical blocks and move the data from the first set of physical blocks to the second set of physical blocks in response to the host requesting that a modified version of the data be written in the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to generate a first mapping portion and a second mapping portion, where the first mapping portion and the second mapping portion correspond to a same data set, and where the first mapping portion and the second mapping portion includes one or more parity bits, receive an update for the same data set, update the first mapping portion and the second mapping portion based on the update, where the second mapping portion is updated non-concurrently to updating the first mapping portion, and where the updating includes flipping a parity bit of the one or more parity bits, and determine whether the one or more parity bits of the first mapping portion matches the one or more parity bits of the second mapping portion.

Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The memory device includes at least a first super device and a second super device. Each of the super devices includes a plurality of active zones and a threshold value for a number of cold zones. The controller classifies zones as either a cold zone or hot zone depending the number of resets to the zone. If the number of resets to the zone is greater than a threshold reset value, then the zone is classified as a hot zone, otherwise the zone is classified as a cold zone. The controller is configured to determine that the number of cold zones is greater than the threshold value for a super device and move data from at least one cold zone from the super device to a zone of another super device.

Abstract: The present disclosure generally relates to writing data to streams. A host device can instruct a data storage device to operate in implied streams mode such that the host device does not need to tell the data storage device the specific stream in which to write data. The data storage device would maintain a list of open append points of specific streams. Upon receiving a write command, the data storage device determines whether the write command is for an already open stream, and if so, write to the specific stream. If not, then the data storage device opens a new stream or write the data to an overflow stream.

Abstract: Rather than use one long folding operation to fold data from single-level cell (SLC) blocks into a multi-level cell (MLC) block, a storage system uses a multi-stage folding operation. By breaking up the folding process into stages, SLC blocks involved in an earlier stage can be released prior to a subsequent stage being performed. This can increase performance of the storage system by releasing SLC source blocks sooner and reducing an SLC block budget requirement.

Abstract: Systems and methods described herein synchronize events between various components of storage device during the processing of an exception (i.e., an internal error). The storage device can have a plurality of processors which may each coordinate operations on various domains of storage device processing tasks. An exception occurring in one domain may require input and coordination from other domains within the storage device. Each exception may have a list of predetermined steps needed for completion which are coordinated via a series of sync points placed between exception action clusters which perform a series of specific operations until data or processing from another domain is needed to continue processing. The sync points can be utilized to halt processing in one domain until the other domains are in sync and complete one or more exception action operations. In this way, a streamlined and predictable synchronization between domains may occur during an exception.

Abstract: A semiconductor device package includes a substrate having a top planar surface and a first semiconductor die electrically connected to the top planar surface of the substrate. The first semiconductor die and substrate define a tunnel and a first molding compound encapsulates the first semiconductor die and fills the tunnel. A second molding compound that is separate and distinct from the first molding compound is mounted on a top surface of the first molding compound. The first molding, when in a flowable state, has a viscosity that is lower than a viscosity of the second molding compound when it is in a flowable state.

Abstract: The present disclosure generally relates to more efficient use of a delta buffer. To Utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.

Abstract: The present disclosure generally relates to improved command processing by separating all state machines into multiple groups. Rather than having one general die that can process any command, this disclosure suggests distributed processing commands by having two types of dies. A slave die will contain the flash array and implementation of state machine that is related to fast operations, and will not include state machines of slow operations. A master die will contain implementation of fast state machine (to support fast commands to the flash array that connected to the master die) and implementation of slow command state machine. The master die will have one instance of the slow state machine implementation, but that slow state machine will be able to be loaded with variables that represent the slow states of all the other dies. The commands processing is based the most suitable state machine for the specific command.

Abstract: A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern. The sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies. The sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, thereby reducing read collisions.

Abstract: A fan-out semiconductor device includes stacked semiconductor dies having die bond pads arranged in columns exposed at a sidewall of the stacked semiconductor dies. The stacked dies are encapsulated in a photo imageable dielectric (PID) material, which is developed to form through-hole cavities that expose the columns of bond pads of each die at the sidewall. The through-hole cavities are plated or filled with an electrical conductor to form conductive through-holes coupling die bond pads within the columns to each other.

Abstract: The present disclosure generally relates to aborting a command efficiently using the host memory buffer (HMB). The command contains pointers that direct the data storage device to various locations on the data storage device where relevant content is located. Once the abort command is received, the content of the host pointers stored in the data storage device RAM are changed to point to the HMB. The data storage device then waits until any already started transactions over the interface bus that are associated with the command have been completed. Thereafter, a failure completion command is posted to the host device.