Abstract: The present disclosure generally relates to a magnetic recording system comprising a magnetic recording head. The magnetic recording head comprises a main pole, a shield, and a spintronic device disposed between the main pole and the shield. The spintronic device comprises a field generation layer (FGL) spaced a distance of about 2 nm to about 3 nm from the main pole, a first spacer layer disposed on the FGL, a spin torque layer (STL) disposed on the first spacer layer, a second spacer layer disposed on the STL, and a negative polarization layer (NPL) disposed between the second spacer layer and the shield. The spintronic device has a length of about 17 nm to about 21. During operation, the STL has a magnetization precession of about 16 degrees to about 170 degrees, and the FGL has a magnetization precession of about 60 degrees to about 70 degrees.

Abstract: The present disclosure generally relates to magnetoresistive (MR) devices. The MR device comprises a synthetic antiferromagnetic (SAF) layer that increases exchange coupling field, and in turn, less magnetic noise of such devices. The MR device comprises a first ferromagnetic (FM1) layer and a second ferromagnetic (FM2) layer, in between which is an SAF spacer of RuAl alloy having a B2 crystalline structure which may grow epitaxial on BCC (110) or FCC (111) textures, meaning that the (110) or (111) plane is parallel to the surface of MR device substrate. Further, amorphous layers may be inserted into the device structure to reset the growth texture of the device to a (001), (110), or (111) texture in order to promote the growth of tunneling barrier layers or antiferromagnetic (AF) pinning layers.

Abstract: A key-value storage device may perform an integrity check on a key and/or a value in a key-value pair, prior to transmitting the value from a memory device to a requestor. When the storage device receives a write command to store the value in the memory device, a processor in the storage device may generate authentication data from the key and/or the value in the write command. The processor may store the authentication data and the value in the memory device. When the processor later receives a read command to retrieve the value from the memory device, the processor may perform the integrity check on the key and/or the value using the authentication data.

Abstract: In order to guarantee data validity of data read from a memory device of the data storage device to a host device, a controller of the data storage device may calculate a cyclic redundancy code (CRC) signature of the decoded data and compare the CRC signature of the decoded data with a CRC signature of the data. The CRC signature of the data is generated during a write operation of the data to the memory device. Rather than returning an uncorrectable error correction code error (UECC) error to the host device when the CRC signature of the decoded data does not match the CRC signature of the data, the controller executes the read command again. By using a different buffer to store the decoded data, the controller may confirm whether the error stemmed from the read path or the error was not from the read path.

Abstract: During data storage device operation, data of multiple blocks of a non-volatile memory device, logically grouped as a jumboblock, may be protected by an exclusive or (XOR) signature, where the XOR signature may be used to recover data of a block of the multiple blocks. During a recovery/relocation operation, data of the jumboblock is read from the non-volatile memory device during the recovery of the lost data and again when the data is relocated. However, because the data read during data storage device operation is temporarily stored in a volatile memory device, the controller utilizes the relevant data stored in the volatile memory device and the data stored in the non-volatile memory device to recover corrupted data. Thus, the amount of reads from the non-volatile memory device decreases due to the relevant data is read from the volatile memory device, which may improve data storage device performance.

Abstract: A data storage device includes a laser diode that heats an area of a disk near the read/write head. To mitigate mode hopping, the laser diode is preheated using the laser diode itself, such as by applying a reverse bias to the laser diode, during an interruption in writing of data to the disk. The laser diode is preheated to a temperature that maintains operation of the laser diode within a middle portion of a preselected gain mode and away from abrupt shifts in gain modes.

Abstract: Systems, methods, and data storage devices for using data storage device operational profiles for interface-based performance leveling are described. Data storage devices are connected to a virtual storage manager using network or storage bus connections. Comparisons of the data processing speed and interface speed of each data storage device and its connection may be used to determine an active device operational profile for each data storage device to reach a target aggregate performance. The device operational profiles may be sent to the data storage devices to change their operations, such as the handling of background processes.

Abstract: A disk drive may include a disk, a head actuated over the disk, a spindle motor comprising a plurality of windings and operable to rotate the disk and coupled to a first and a second spindle driver, the first and the second spindle driver coupled in parallel to the plurality of windings. The disk drive further includes one or more processing devices that are configured to detect a BEMF signal corresponding to a velocity and/or a position of the spindle motor, control, based on detecting the BEMF signal, commutation of the plurality of windings of the spindle motor using the first and the second spindle driver, and wherein the plurality of windings are commutated at or near the same time or in a sequential manner during one or more of a spin up and a spin down routine of the spindle motor.

Abstract: The present disclosure generally relates to spin-orbit torque (SOT) magnetic tunnel junction (MTJ) devices comprising a doped bismuth antimony (BiSbE) layer having a (012) orientation. The devices may include magnetic write heads, read heads, or MRAM devices. The dopant in the BiSbE layer enhances the (012) orientation. The BiSbE layer may be formed on a texturing layer to ensure the (012) orientation, and a migration barrier may be formed over the BiSbE layer to ensure the antimony does not migrate through the structure and contaminate other layers. A buffer layer and interlayer may also be present. The buffer layer and the interlayer may each independently be a single layer of material or a multilayer of material. The buffer layer and the interlayer inhibit antimony (Sb) migration within the doped BiSbE layer and enhance uniformity of the doped BiSbE layer while further promoting the (012) orientation of the doped BiSbE layer.

Abstract: The present disclosure generally relates to a bismuth antimony (BiSb) based STO (spin torque oscillator) sensor. The STO sensor comprises a SOT device and a magnetic tunnel junction (MTJ) structure. By utilizing a BiSb layer within the SOT device, a larger spin Hall angle (SHA) can be achieved, thereby improving the efficiency and reliability of the STO sensor.

Abstract: The present disclosure generally relates to a dual free layer (DFL) read head and methods of forming thereof. In one embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a stripe height of the DFL sensor, depositing a rear bias (RB) adjacent to the DFL sensor, defining a track width of the DFL sensor and the RB, and depositing synthetic antiferromagnetic (SAF) soft bias (SB) side shields adjacent to the DFL sensor. In another embodiment, a method of forming a DFL read head comprises depositing a DFL sensor, defining a track width of the DFL sensor, depositing SAF SB side shields adjacent to the DFL sensor, defining a stripe height of the DFL sensor and the SAF SB side shield, depositing a RB adjacent to the DFL sensor and the SAF SB side shield, and defining a track width of the RB.

Abstract: Some data storage devices select blocks of memory from a free block pool and randomly allocate the blocks as primary and secondary blocks to redundantly store data in a write operation. However, some blocks, such as blocks on the edge of a plane, may not serve well as primary blocks. One example data storage device presented herein addresses this problem by allocating such blocks as secondary blocks instead of primary blocks.

Abstract: A data storage device may include a media comprising a magnetic recording layer and a heat-assisted magnetic recording (HAMR) head for writing to the magnetic recording layer, the HAMR head comprising: a waveguide, a main pole comprising a main-pole surface facing the magnetic recording layer, a near-field transducer (NFT) situated between the main pole and the waveguide, and a transparent overcoat. The NFT comprises a main body and a micropillar. The micropillar comprises a micropillar surface facing the magnetic recording layer. A first distance between the micropillar surface and the media is less than a second distance between the main-pole surface and the media. The transparent overcoat is situated on the main-pole surface and the micropillar surface.

Abstract: The present disclosure is generally related to a magnetic recording device comprising a magnetic recording head. The magnetic recording head comprises a main pole, a hot seed layer, and a spintronic device disposed between the main pole and the hot seed layer. The spintronic device comprises two field generation layers (FGLs), two spin polarization layers (SPLs), and two spin kill layers. The second SPL of the spintronic device drives the second FGL. The spintronic device further comprises one or more optional thin negative beta material layers, such as layers comprising FeCr, disposed in contact with at least one of the spin kill layers. When electric current is applied, the spin kill layers and optional negative beta material layers eliminate or reduce any spin torque between the FGLs and the SPLs.

Abstract: With ever-increasing capacities and performance demanded in new storage devices, the number of control table data entries are increased to store more updates stemming from the increased number of read and/or write operations. To avoid becoming a bottleneck, devices, such as storage devices, and other similar methods and systems as described herein efficiently manage control table sets to reduce latency. This can be accomplished by designating a specific position for each control table set and storing updates to such control table sets in a designated position. Furthermore, data can be efficiently kept in the volatile memory, such as SRAM, or evicted from the volatile memory to the non-volatile memory, such as NAND. Determinations can occur for when the read/write operations should be performed using volatile memory or non-volatile memory. These determinations can be decided dynamically and based on the storage device state and incoming workload, resulting in lower overall latencies.

Abstract: A system includes at least one memory controller that partitions at least one memory into a plurality of nodes. Blast zones are formed that each include a predetermined number of nodes. Cache lines are erasure encoded to be stored in one or more blast zones with at least two nodes in a blast zone storing respective portions of a cache line and at least one node in the blast zone storing a parity portion. In one aspect, it is determined that data stored in one or more nodes of a blast zone needs to be reconstructed and stored in one or more spare nodes designated to replace the one or more nodes. Erasure decoding is performed using data from one or more other nodes in the blast zone to reconstruct the data for storage in the one or more spare nodes.

Abstract: The present disclosure is generally related to a magnetic recording device comprising a magnetic recording head. The magnetic recording head comprises a main pole, a shield, and a spintronic device disposed between the main pole and the shield. The spintronic device comprises two field generation layers (FGLs), two spin polarization layers (SPLs), and two spin kill layers. The spintronic device further comprises one or more optional thin negative beta material layers, such as layers comprising FeCr, disposed in contact with at least one of the spin kill layers. When electric current is applied, the spin kill layers and optional negative beta material layers eliminate or reduce any spin torque between the FGLs and the SPLs.

Abstract: Various illustrative aspects are directed to a data storage device comprising a disk, a read/write head configured to read data from and write data to the disk, a laser diode (LD) coupled to a nearfield transducer configured to heat an area of the disk near the read/write head, a first resistive temperature detector (RTD), a second RTD, and one or more processing devices configured to: apply a laser bias to the LD during a write operation; obtain a plurality of differential signal measurements, based at least in part on a plurality of measurements from each of the first and second RTDs; and adjust the laser bias applied to the LD, based at least in part on comparing the plurality of differential signal measurements to a target value for the differential signal.

Abstract: In addition to word line related short circuits within the blocks of the array structure of a non-volatile memory device, such as NAND memory, word line related shorts can also occur in the routing for supplying the word lines of the memory blocks. Depending on the layout of the routing, some shorts for the word lines associated with one block can affect other blocks of the memory array. In particular, if the routing of a pair of adjacent local supply lines are adjacent to a global supply line, a short between the pair of adjacent local supply lines for one block can lead, through the global supply line, to defects in another of the block. Techniques are presented for detecting these layout related problematic word lines.

Abstract: The memory device includes a plurality of memory cells which are arranged in a plurality of word lines. The plurality of word lines includes a selected group of word lines to be erased in an erasing operation. The memory device also includes circuitry that is configured to erase the memory cells of the selected group of word lines in at least one erase loop. The at least one erase loop includes an erase pulse, an erase-verify operation, and an analog bitscan operation. The circuitry is configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to set at least one erase parameter based on the output of the analog bitscan operation.